XRT74L74 Datasheet, PDF (123/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
the local µP must to write a “1” to bit 7 (SendOAM)
within the TxCP OAM Register as depicted below.
TxCP OAM Register (Address = 61h)
BIT 7
SendOAM
Semaphore
BIT 6
RO
BIT 5
RO
BIT 4
RO
BIT 3
Unused
RO
BIT 2
RO
BIT 1
RO
BIT 0
RO
If the local µP writes a “1” bit 7 (or 1xxxxxxxb) to the
TxCP OAM Register; then the Transmit Cell Proces-
sor will read-in the contents of the “Transmit OAM
Cell” buffer, and form it into a cell. This OAM cell will
then be routed to the HEC Byte Calculator and Cell
Scrambler within the Transmit Cell Processor block,
prior to transmittal to the Transmit PLCP Processor
(or Transmit DS3 Framer). Bit 7 of the TxCP OAM
Register will be reset (to “0”) upon completion of the
transmission of the OAM cell. This bit may also be
polled in order to determine whether or not the OAM
cell has been sent.
The number of valid cells (e.g., user and OAM cells)
that have been generated and transmitted to the
Transmit PLCP Processor or the Transmit DS3
Framercan be monitored . The Transmit Cell Proces-
sor increments the contents of the “PMON Transmit-
ted Valid Cell Count (MSB and LSB)” Registers (Ad-
dress = 3Ah, and 3Bh) for each valid cell that it gener-
ates. These two registers are “Reset-upon-Read”
registers that when concatenated present a 16-bit
representation of the total number of “valid cells” gen-
erated and transmitted by the Transmit Cell Proces-
sor, since the last read of these registers. The bit-for-
mat of these two registers follows:
PMON Transmitted Valid Cell Count—MSB (Address = 3Ah)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
Tx Valid Cell Count—High Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON Transmitted Valid Cell Count—LSB (Address = 3Bh)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
Tx Valid Cell Count—Low Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
3.2.2.4 Idle Cell Processing
Whenever the TxFIFO (within the Transmit UTOPIA
Interface block) does not contain a complete cell, the
Transmit Cell Processor will automatically generate
and process Idle Cells. The contents of these Idle
Cells can be customized or the default values that are
provided by the UNI chip can be used. The contents
of these Idle Cells can be customized by program-
ming six different registers:
• TxCP Idle Cell Pattern—Header Byte 1
• TxCP Idle Cell Pattern—Header Byte 2
• TxCP Idle Cell Pattern—Header Byte 3
• TxCP Idle Cell Pattern—Header Byte 4
• TxCP Idle Cell Pattern—Header Byte 5
• TxCP Transmit Cell Payload
Table 10 presents the Bit Format of each of these
Registers and Table 11 presents the Address and
Default values of these cells.
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