XRT74L74 Datasheet, PDF (6/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
URE THE XRT74L74 TO TRANSMIT A YELLOW ALARM TO THE REMOTE TERMINAL EQUIPMENT ................................................ 218
TABLE 38: DESCRIPTION OF METHOD 2 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ................................................................... 219
FIGURE 66. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD
2) ....................................................................................................................................................................................... 220
TABLE 39: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE OF THE TXOHFRAME PULSE)
TO THE DS3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT74L74........................................................................ 221
FIGURE 67. BEHAVIOR OF TRANSMIT OVERHEAD DATA INPUT INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT
(FOR METHOD 2)................................................................................................................................................................. 223
5.2.3 THE TRANSMIT DS3 HDLC CONTROLLER ........................................................................................................... 223
TX DS3 FEAC REGISTER (ADDRESS = 0X32) ............................................................................................................ 224
TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31) ................................................... 224
TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31) ................................................... 224
FIGURE 68. A FLOW CHART DEPICTING HOW TO TRANSMIT A FEAC MESSAGE VIA THE FEAC TRANSMITTER........................................ 225
FIGURE 69. LAPD MESSAGE FRAME FORMAT..................................................................................................................................... 226
TABLE 40: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFORMATION PAYLOAD ...... 226
TRANSMIT DS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ....................................................................... 227
TABLE 41: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ................................................................ 227
TRANSMIT DS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ....................................................................... 227
TABLE 42: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ................................................................ 227
TRANSMIT DS3 LAPD STATUS/INTERRUPT REGISTER (ADDRESS = 0X34)................................................................... 228
FIGURE 70. FLOW CHART DEPICT HOW TO USE THE LAPD TRANSMITTER ............................................................................................ 229
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 230
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................................................... 230
5.2.4 THE TRANSMIT DS3 FRAMER BLOCK .................................................................................................................. 230
FIGURE 71. A SIMPLE ILLUSTRATION OF THE TRANSMIT DS3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO OTHER FUNCTIONAL BLOCKS
231
TX DS3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................................. 232
TABLE 43: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 7 (TX YELLOW ALARM) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND
THE RESULTING TRANSMIT DS3 FRAMER BLOCK’S ACTION ................................................................................................... 232
TABLE 44: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 6 (TX X-BITS) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE RE-
SULTING TRANSMIT DS3 FRAMER BLOCK’S ACTION.............................................................................................................. 232
TABLE 45: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 5 (TX IDLE) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE RESULT-
ING TRANSMIT DS3 FRAMER ACTION ................................................................................................................................... 233
TABLE 46: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 4 (TX AIS PATTERN) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE
RESULTING TRANSMIT DS3 FRAMER BLOCK’S ACTION.......................................................................................................... 233
TABLE 47: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (TX LOS) WITHIN THE TX DS3 CONFIGURATION REGISTER, AND THE RESULT-
ING TRANSMIT DS3 FRAMER BLOCK’S ACTION ..................................................................................................................... 234
TX DS3 M-BIT MASK REGISTER, ADDRESS = 0X35 .................................................................................................... 234
TX DS3 F-BIT MASK1 REGISTER, ADDRESS = 0X36................................................................................................... 235
TX DS3 F-BIT MASK2 REGISTER, ADDRESS = 0X37................................................................................................... 235
TX DS3 F-BIT MASK3 REGISTER, ADDRESS = 0X38................................................................................................... 235
TX DS3 F-BIT MASK4 REGISTER, ADDRESS = 0X39................................................................................................... 235
5.2.5 THE TRANSMIT DS3 LINE INTERFACE BLOCK.................................................................................................... 235
FIGURE 72. APPROACH TO INTERFACING THE XRT74L74 FRAMER IC TO THE XRT73L00 DS3/E3/STS-1 TRANSMITTER LIU (ONE CHANNEL
SHOWN) .............................................................................................................................................................................. 236
FIGURE 73. A SIMPLE ILLUSTRATION OF THE TRANSMIT DS3 LIU INTERFACE BLOCK ............................................................................ 237
FIGURE 74. THE BEHAVIOR OF TXPOS AND TXNEG SIGNALS DURING DATA TRANSMISSION WHILE THE TRANSMIT DS3 LIU INTERFACE IS OP-
ERATING IN THE UNIPOLAR MODE ........................................................................................................................................ 237
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 238
TABLE 48: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O CONTROL REGISTER AND THE
TRANSMIT DS3 FRAMER LINE INTERFACE OUTPUT MODE .................................................................................................... 238
FIGURE 75. ILLUSTRATION OF AMI LINE CODE .................................................................................................................................... 239
FIGURE 76. ILLUSTRATION OF TWO EXAMPLES OF B3ZS ENCODING ..................................................................................................... 239
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 240
TABLE 49: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR LINE CODE THAT IS OUTPUT
BY THE TRANSMIT DS3 LIU INTERFACE BLOCK .................................................................................................................... 240
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................................. 240
TABLE 50: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE TXLINECLK
CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ................................................................................................... 240
FIGURE 77. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG ARE CONFIGURED TO BE
UPDATED ON THE RISING EDGE OF TXLINECLK ..................................................................................................................... 241
FIGURE 78. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG ARE CONFIGURED TO BE
UPDATED ON THE FALLING EDGE OF TXLINECLK ................................................................................................................... 241
5.2.6 TRANSMIT SECTION INTERRUPT PROCESSING ................................................................................................. 241
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