XRT74L74 Datasheet, PDF (117/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
be disabled. A “1” must be written to this bit in order
to enable this interrupt.
TxUT Interrupt Enable /Status Register (Address-6Eh)
BIT 7
TxFIFO
Reset
R/W
BIT 6
Discard
Upon Parity
Error
R/W
BIT 5
TxUT Parity
Error
Interrupt
Enable
R/W
BIT 4
TxFIFO
Overrun
Interrupt
Enable
R/W
BIT 3
TCOCA
Interrupt
Enable
R/W
BIT 2
TxUT Parity
Error
Interrupt
Status
RUR
BIT 1
TxFIFO
Overrun
Interrupt
Status
RUR
BIT 0
TCOCA
Interrupt
Status
RUR
3.2 Transmit Cell Processor
3.2.1 Brief Description of the Transmit
Cell Processor
The Transmit Cell Processor reads in cells from the
Transmit UTOPIA FIFO (TxFIFO) within the Transmit
UTOPIA Interface block. Immediately after reading in
the cell from the TxFIFO, the Transmit Cell Processor
will verify the “Data Path Integrity Check” pattern
(located in octet # 5, within this cell). Afterwards, the
Transmit Cell Processor optionally computes and
inserts the HEC byte into each cell and optionally
scrambles the cell payload bytes. When the TxFIFO
does not contain a full cell, the Transmit Cell Processor
generates a programmable idle (or unassigned) cell
and inserts it in the transmit stream. The Transmit Cell
Processor provides the capability to write an “out-
bound” OAM cell into the “Transmit OAM Cell” buffer,
and to transmit this OAM cell, upon demand. Addition-
ally, the Transmit Cell Processor is also equipped with a
serial input port which provides a means to externally
insert the value of the GFC (Generic Flow Control)
field for each outbound cell. Figure 15 presents a
simple illustration of the Transmit Cell Processor
block and the associated external pins.
FIGURE 15. SIMPLE ILLUSTRATION OF THE TRANSMIT
CELL PROCESSOR BLOCK AND THE ASSOCIATED
EXTERNAL PINS
To Transmit PLCP
Processor
TxCellTxed
TxGFCClk
TxGFCMSB
TxGFC
Transmit Cell
Processor
From Transmit Utopia
Interface
Figure 15 presents a functional block diagram of the
Transmit Cell Processor.
3.2.2 Functional Description of Transmit
Cell Processor
The Transmit Cell Processor consists of the following
functional blocks.
• Configuration and Status Register
• Controller
• HEC Byte Calculator
• OAM Cell Processor
• Cell Scrambler
• IDLE Cell Generator
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