XRT74L74 Datasheet, PDF (250/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
REV. P1.1.1
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
ADVANCED CONFIDENTIAL
FIGURE 84. ILLUSTRATION OF TWO EXAMPLES OF B3ZS DECODING
Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
00 V
Line Signal
RxPOS
RxNEG
B 0V
5.3.1.2.3 Line Code Violations
The Receive DS3 LIU Interface block will also check
the incoming DS3 data stream for line code viola-
tions. For example, when the Receive DS3 LIU Inter-
face block detects a valid bipolar violation (e.g., in
B3ZS line code), it will substitute three zeros into the
binary data stream. However, if the bipolar violation
is invalid, then an LCV (Line Code Violation) is
flagged and the PMON LCV Event Count Register
(Address = 0x50 and 0x51) will also be incremented.
Additionally, the LCV-One Second Accumulation Reg-
isters (Address = 0x6E and 0x6F) will be increment-
ed. For example: If the incoming DS3 data is B3ZS
encoded, the Receive DS3 LIU Interface block will al-
so increment the LCV One Second Accumulation
Register if three (or more) consecutive zeros are re-
ceived.
II/O CONTROL REGISTER (ADDRESS = 0X01)
5.3.1.2.4 RxLineClk Clock Edge Selection
The incoming unipolar or bipolar data, applied to the
RxPOS and the RxNEG input pins are clocked into
the Receive DS3 LIU Interface block via the RxLi-
neClk signal. The Framer IC allows the user to spec-
ify which edge (e.g, rising or falling) of the RxLineClk
signal will sample and latch the signal at the RxPOS
and RxNEG input signals into the Framer IC. This
feature was included in the XRT74L74 design to in-
sure that the user can always meet the RxPOS and
RxNEG to RxLineClk set-up and hold time require-
ments. This selection is made by writing the appro-
priate data to bit 1 of the I/O Control Register, as de-
picted below.
BIT 7
BIT 6
BIT 5
BIT 4
Disable
TxLOC
R/W
1
LOC
RO
0
Disable
RxLOC
R/W
1
AMI/ZeroSup*
R/W
0
Table 52 depicts the relationship between the value
of this bit-field to the sampling clock edge of RxLi-
neClk.
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
TxLine CLK
Invert
R/W
0
BIT 1
RxLine CLK
Invert
R/W
0
BIT 0
Reframe
R/W
0
248