XRT74L74 Datasheet, PDF (13/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
FIGURE 170. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74
FOR MODE 4 (NIBBLE-PARALLEL/LOOP-TIMED) OPERATION .................................................................................................. 402
FIGURE 171. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (MODE 4 OPERATION)
403
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 403
FIGURE 172. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74
FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIME/FRAME-SLAVE) OPERATION ............................................................................ 404
FIGURE 173. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (E3 MODE 5 OPER-
ATION) ................................................................................................................................................................................ 405
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 405
FIGURE 174. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74
FOR MODE 6 OPERATION .................................................................................................................................................... 406
FIGURE 175. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (E3 MODE 6 OPER-
ATION) ................................................................................................................................................................................ 407
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 407
7.2.2 THE TRANSMIT OVERHEAD DATA INPUT INTERFACE ...................................................................................... 407
FIGURE 176. THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK.............................................................................................. 408
TABLE 87: THE OVERHEAD BITS WITHIN THE E3 FRAME AND THEIR POTENTIAL SOURCES ...................................................................... 409
TABLE 88: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ................................................................... 411
FIGURE 177. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 1) ......... 412
TABLE 89: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE "TXOHFRAME" WAS LAST SAMPLED
"HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED............................................................................................ 413
FIGURE 178. ILLUSTRATION OF THE SIGNAL THAT MUST OCCUR BETWEEN THE TERMINAL EQUIPMENT AND THE XRT74L74, IN ORDER TO CON-
FIGURE THE XRT74L74 TO TRANSMIT A YELLOW ALARM TO THE REMOTE TERMINAL EQUIPMENT ........................................... 415
TABLE 90: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ................................................................... 416
FIGURE 179. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 2) ......... 417
TABLE 91: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE OF THE TXOHFRAME PULSE)
TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT74L74 .......................................................................... 418
FIGURE 180. BEHAVIOR OF TRANSMIT OVERHEAD DATA INPUT INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT
FOR METHOD 2 ................................................................................................................................................................... 420
7.2.3 THE TRANSMIT E3 HDLC CONTROLLER.............................................................................................................. 420
FIGURE 181. LAPD MESSAGE FRAME FORMAT................................................................................................................................... 421
TABLE 92: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFORMATION PAYLOAD ...... 422
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33).......................................................................... 422
TABLE 93: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE ................................................................ 423
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................................................ 423
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ...................................................................................... 423
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33).......................................................................... 424
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .......................................................................... 424
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .......................................................................... 425
FIGURE 182. FLOW CHART DEPICTING HOW TO USE THE LAPD TRANSMITTER (LAPD TRANSMITTER IS CONFIGURED TO RE-TRANSMIT THE LAPD
MESSAGE FRAME REPEATEDLY AT ONE-SECOND INTERVALS) ............................................................................................... 426
FIGURE 183. FLOW CHART DEPICTING HOW TO USE THE LAPD TRANSMITTER (LAPD TRANSMITTER IS CONFIGURED TO TRANSMIT A LAPD MES-
SAGE FRAME ONLY ONCE).................................................................................................................................................... 427
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04).......................................................................................... 428
7.2.4 THE TRANSMIT E3 FRAMER BLOCK..................................................................................................................... 428
FIGURE 184. THE TRANSMIT E3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO OTHER FUNCTIONAL BLOCKS ................................... 429
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................................................ 430
TABLE 94: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3 CONFIGURATION REGISTER, AND THE
RESULTING TRANSMIT E3 FRAMER BLOCK’S ACTION ............................................................................................................ 430
TABLE 95: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION REGISTER, AND THE RESULTING
TRANSMIT E3 FRAMER BLOCK’S ACTION.............................................................................................................................. 430
7.2.5 THE TRANSMIT E3 LINE INTERFACE BLOCK ...................................................................................................... 431
FIGURE 185. APPROACH TO INTERFACING THE XRT74L74 FRAMER IC TO THE XRT73L00 DS3/E3/STS-1 LIU .................................. 432
FIGURE 186. THE TRANSMIT E3 LIU INTERFACE BLOCK ...................................................................................................................... 433
FIGURE 187. THE BEHAVIOR OF TXPOS AND TXNEG SIGNALS DURING DATA TRANSMISSION WHILE THE TRANSMIT DS3 LIU INTERFACE IS OP-
ERATING IN THE UNIPOLAR MODE ........................................................................................................................................ 433
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 434
TABLE 96: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O CONTROL REGISTER AND THE
TRANSMIT E3 FRAMER LINE INTERFACE OUTPUT MODE ....................................................................................................... 434
FIGURE 188. AMI LINE CODE ............................................................................................................................................................. 435
FIGURE 189. TWO EXAMPLES OF HDB3 ENCODING............................................................................................................................. 435
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 436
TABLE 97: THE RELATIONSHIP BETWEEN BIT 4 (AMI/HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR LINE CODE THAT IS OUTPUT
XI