XRT74L74 Datasheet, PDF (114/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
1. The Transmit UTOPIA Data bus is configured to be
16 bits wide. Hence, the data which the ATM Layer
processor places on the Transmit UTOPIA Data
bus, is expressed in terms of 16-bit words (e.g.,
W0–W26).
2. The Transmit UTOPIA Interface Block is configured
to handle 54 bytes/cell. Hence, Figure 14 illus-
trates the ATM Layer processor writing 27 words
(e.g., W0 through W26) for each ATM cell.
In Figure 14 , the ATM Layer processor is initially writ-
ing ATM cell data to the Transmit UTOPIA Interface
block within UNI #2 (TxUAddr[4:0] = 02h). However,
the ATM Layer processor is also polling the Transmit
UTOPIA Interface block within UNI #1 (TxUAddr[4:0]
= 00h) and some “non-existent” device at TxU-
Addr[4:0] = 1Fh. The ATM Layer processor completes
its writing of the cell to UNI #1 at clock edge #4. After-
wards, the ATM Layer processor will cease to write
any more cell data to UNI #1, and will begin to write
this data into UNI #2 (TxUAddr[4:0] = 02h). The ATM
Layer processor will indicate its intentions to select a
new UNI device for writing by negating the TxUEn
signal, at clock edge #5 (see the shaded portion of
Figure 14 ). At this time, UNI #1 will notice two things:
1. The UTOPIA Address for the Transmit UTOPIA
Interface block, within UNI #1 is on the Transmit
UTOPIA Address bus (TxUAddr[4:0] = 00h).
2. The TxUEn signal has been negated.
UNI #1 will interpret this signaling as an indication
that the ATM Layer processor is going to be perform-
ing write operations to it. Afterwards, the ATM Layer
processor will begin to write ATM cell data into Trans-
mit UTOPIA Interface block, within UNI #1.
3.1.2.5 Transmit UTOPIA Interrupt Servicing
The Transmit UTOPIA Interface block will generate in-
terrupts upon the following conditions:
• Detection of parity errors
• Change of cell alignment (e.g., the detection of
“runt” cells)
• TxFIFO Overrun
If one of these conditions occur and if that particular
condition is enabled for interrupt generation, then
when the local µP/µC reads the UNI Interrupt status
register, as shown below; it should read “xxxx1xxxb”
(where the b suffix denotes a binary expression, and
the “x” denotes a “don’t care” value).
UNI Interrupt Status Register (Address = 05h)
BIT 7
Rx DS3
Interrupt
Status
RO
x
BIT 6
Rx PLCP
Interrupt
Status
RO
x
BIT 5
Rx CP
Interrupt
Status
RO
x
BIT 4
Rx UTOPIA
Interrupt
Status
RO
x
BIT 3
TxUTOPIA
Interrupt
Status
RO
1
BIT 2
TxCP
Interrupt
Status
RO
x
BIT 1
TxDS3 Inter-
rupt
Status
RO
x
BIT 0
One Sec
Interrupt
Status
RUR
x
At this point, the local µC/µP has determined that the
Transmit UTOPIA Interface block is the source of the
interrupt, and that the Interrupt Service Routine
should branch accordingly.
The next step in the interrupt service routine should
be to determine which of the three Transmit UTOPIA
Interface Block interrupt conditions has occurred and
is causing the Interrupt request. In order to accomplish
this, the local µP/µC should now read the TxUT Inter-
rupt Enable/Status Register, which is located at ad-
dress 6Eh within the UNI device. The bit format of this
register is presented below.
TxUT Interrupt Enable /Status Register (Address-6Eh)
BIT 7
TFIFO
Reset
R/W
BIT 6
Discard
Upon
PErr
R/W
BIT 5
TPerr
Interrupt
Enable
R/W
BIT 4
TxFIFO
ErrInt
Enable
R/W
BIT 3
TCOCA
Interrupt
Enable
R/W
BIT 2
TPErr
Interrupt
Status
RUR
BIT 1
TxFIFO
OverInt
Status
RUR
BIT 0
TCOCA
Interrupt
Status
RUR
The “TxUT Interrupt Enable/Status” Register has
eight bit-fields. However, only six of these bit fields
are relevant to interrupt processing. Bits 0–2 are the
interrupt status bits and bits 3–5 are the interrupt en-
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