XRT74L74 Datasheet, PDF (178/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
trates the ATM Layer processor reading in 27
words (W0 through W26) for each ATM cell.
In Figure 39 , the ATM Layer processor is just finishing
up its reading of an ATM cell. Prior to clock edge #2,
the RxFIFO does not contain enough ATM cell data to
make up at least one cell. Hence, the Receive UTO-
PIA Interface block negates the RxUClav signal. The
ATM Layer processor detects that the RxUClav signal
has toggled “low”; at clock edge #2. Hence, the ATM
Layer processor will finish reading in the current ATM
cell; from the Receive UTOPIA Interface block of the
UNI (e.g., words W25 and W26). Afterwards, the ATM
Layer processor will negate the RxUEn signal and will
cease to read in anymore ATM cell data from the
Receive UTOPIA Interface block; until RxUClav tog-
gles “high” again.
The RxFIFO accumulates enough cell data to make
up a complete ATM cell shortly before clock edge #5.
At this point the Receive UTOPIA Interface block
reflects this fact by asserting the RxUClav signal. The
ATM Layer processor detects that the RxUClav signal
has toggled “high” at clock edge #5. Consequently,
the ATM Layer processor then asserts the RxUEn
signal (e.g., toggles it “low”) after clock edge #5. The
Receive UTOPIA Interface block detects the fact that
the RxUEn input pin has been asserted at clock edge
#6. The Receive UTOPIA Interface block then re-
sponds to this signaling by placing the first word of
the next cell on the Receive UTOPIA Data bus. After-
wards, the ATM Layer processor continues to read in
the remaining words of this cell.
4.4.2.2.1.3 Resetting the RxFIFO via Software
Command
The UNI allows for reseting the RxFIFO, via Software
Command, without the need to implement a master
reset of the entire UNI device. This can be accom-
plished by writing the appropriate data to bit 6
(RxFIFO Reset) of the Receive UTOPIA Interrupt En-
able/Status Register as depicted below.
Receive UTOPIA—Interrupt/Status Register (Address—6Bh)
BIT 7
Unused
R/O
BIT 6
RxFIFO
Reset
R/W
BIT 5
RxFIFO
Overrun
Interrupt
Enable
R/W
BIT 4
RxFIFO
Underrun
Interrupt
Enable
R/W
BIT 3
RCOCA
Interrupt
Enable
R/W
BIT 2
RxFIFO
Overrun
Interrupt
Enable
RUR
BIT 1
RxFIFO
Underrun
Interrupt
Enable
RUR
BIT 0
RxFIFO
COCA
Int. Status
RUR
Once the RxFIFO has been reset, then the contents of
the RxFIFO will be “flushed” and the Receive FIFO
Status register will reflect the “RxFIFO Empty” status.
4.4.2.2.1.4 Monitoring the RxFIFO Status
The local µP has the ability to poll and monitor the
status of the RxFIFO via the Receive UTOPIA FIFO
Status Register. The bit format of this register is
presented below.
Receive UTOPIA FIFO Status Register (Address = 6Dh)
BIT 7
RO
BIT 6
RO
BIT 5
BIT 4
Unused
RO
RO
BIT 3
RO
BIT 2
RO
BIT 1
RxFIFO Full
RO
BIT 0
RxFIFO Empty
RO
The following tables define the values for Bits 1 and 0
and the corresponding meaning.
RxFIFO Full
RXFIFO FULL (BIT 1)
0
1
MEANING
RxFIFO is not full.
RxFIFO is full, and if the next operation by the ATM Layer processor is not a read operation,
then the RxFIFO could be overrun.
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