XRT74L74 Datasheet, PDF (119/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
Cell Buffer”. When the local µP decides to transmit
the OAM cell to the “Far-End” Terminal, it writes a “1”
to a certain register bit. The Transmit Cell Processor
will then proceed to read in the contents of the “Trans-
mit OAM Cell” buffer, and form a cell from this data.
This OAM cell will be subsequently processed like any
user or Idle cell (e.g., processed through the HEC
Byte Calculator and Cell Scrambler) and then routed to
the Transmit PLCP Processor (or Transmit DS3 Fram-
er).
As mentioned earlier, the Transmit Cell Processor will
perform a “Data Path Integrity Check” on all user cells
that it reads from the TxFIFO. More specifically, the
Transmit Cell Processor will look for a specific data
pattern that should be residing within octet #5 of
these cells. The purpose of this test is to verify the in-
tegrity of the communication link throughout the “ATM
Layer processor” system. This “Data Path Integrity
Pattern” was written into the cell by the Receive Cell
Processor of another UNI, prior to its entry into the
“ATM Layer processor” system. If the Transmit Cell
Processor detects a discrepancy between the con-
tents of octet #5 and the expected pattern, then the
Transmit Cell Processor will generator a “Data Path
Integrity Check” error interrupt. After the Transmit Cell
Processor has completed checking for the “Data Path
Integrity Check” pattern; within a given cell, it will (op-
tionally) overwrite this pattern by inserting the HEC
byte.
The Transmit Cell Processor will inform external
circuitry when a cell has been transmitted from the
Transmit Cell Processor to either the Transmit PLCP
Processor or the Transmit DS3 Framer, by pulsing the
“TxCellTxed” output pin.
3.2.2.1 HEC Byte Calculation and Insertion
The “HEC Byte Calculator” takes the first four bytes of
each cell and computes a CRC-8 value via the gener-
ating polynomial x⁸ + x² + x + 1. The user has the op-
tion to have the coset polynomial x⁶ + x⁴ + x² + 1
modulo-2 added to the CRC-8 byte and, instead in-
sert this newly computed value into byte 5 of the cell
before transmission. The following are additional op-
tions regarding the “HEC Byte Calculator”.
• HEC Byte Calculation and Insertion Enable/Disable
for user and OAM cells.
• HEC Byte Calculation and Insertion Enable/Disable
for Idle Cells.
• Inserting errors into the HEC byte, for chip/equipment
testing purposes.
The implementation and result of selecting each of
these options are presented below.
3.2.2.1.1 Configuring the HEC Byte Calculator
for User and OAM Cells
The “HEC Byte Calculation and Insertion” feature can
be enabled or disabled for user and OAM cells. This
option is excercised by writing the appropriate value
to Bit 5 of the TxCP Control Register, as depicted be-
low.
TxCP Control Register (Address = 60h)
BIT 7
Scrambler
En
R/W
1
BIT 6
Coset
Enable
R/W
1
BIT 5
HEC Insert
Enable
R/W
x
BIT 4
TDPChk
Pattern
R/W
1
BIT 3
GFC Insert
Enable
R/W
0
BIT 2
TDPErr
Interrupt
Enable
R/W
0
BIT 1
Idle Cell
HEC CalEn
R/W
1
BIT 0
TDPErr
Interrupt
Status
RUR
0
If this feature is disable, then the HEC byte will not be
computed and the contents within the fifth octet posi-
tion of each cell (e.g., typically the “Data Path Integrity
Check” pattern) will be transmitted to the Transmit PLCP
(or Transmit DS3 Framer) block as is. The following ta-
ble relates the content of this bit-field to the “HEC Byte
Calculator’s” handling of valid (e.g., user or OAM)
cells.
TABLE 8: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT-FIELD 5 (HEC INSERT ENABLE) WITHIN THE TXCP
CONTROL REGISTER, AND THE HEC BYTE CALCULATOR’S HANDLING OF VALID CELLS
HEC INSERT ENABLE
RESULT
0
HEC Byte Calculation is disabled and the 5th byte is transmitted to the Transmit PLCP Block
(or Transmit DS3 Framer) as is
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