XRT74L74 Datasheet, PDF (17/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PIN DESCRIPTION
PIN#
NAME
Microprocessor Interface
AB3
A0
AA4
A1
AA1
A2
AA2
A3
Y1
A4
Y2
A5
Y3
A6
V4
NibbleIntf
AC7
D0
AD6
D1
AE5
D2
AF4
D3
AC5
D4
AD4
D5
AE3
D6
AF2
D7
AE2
ALE_AS
AB1
CS
TYPE
DESCRIPTION
I
Address Bus Input (Microprocessor Interface):
These pins are used to select the on-chip Framer/UNI registers and RAM space
for READ/WRITE operations with the “local” microprocessor.
I
Nibble Interface Select Input pin:
This input pin permits the user to configure the Transmit Payload Data Input
Interface and the Receive Payload Data Output Interface blocks to operate in
either the "Serial" or the "Nibble-Parallel" Mode.
Setting this input pin "high" configures each of these blocks to operate in the Nib-
ble-Parallel Mode. In this mode, the "Transmit Payload Data Input Interface"
block will accept the "outbound" payload data (from the local terminal equip-
ment) in a "nibble-parallel" manner via the "TxNib[3:0]" input pins. Further, the
Receive Payload Data Output Interface block will output "inbound" payload data
(to the local terminal equipment) in a "nibble-parallel" via the "RxNib[3:0] output
pins.
Setting this input pin "low" configures each of these blocks to operate in the
Serial Mode. In this mode, the Transmit Payload Data Input Interface block will
accept the "outbound" payload data (from the local terminal equipment) in a
"serial" manner via the "TxSer_n" input pin. Further, the Receive Payload Data
Output Interface block will output the "inbound" payload data (to the local termi-
nal equipment) in a serial manner, via the "RxSer_n" output pin.
NOTE: This input pin is only active if the XRT74L74 device has been configured
to operate in the Clear-Channel Framer Mode.
I/O ^{Bi-Directional Data Bus (Microprocessor Interface Section):}
These pins function as the Microprocessor Interface bi-directional data bus and is
intended to be interfaced to the “local” microprocessor. This pin is inactive if the
Microprocessor Interface block is configured to operate over an 8 bit data bus.
I
Address Latch Enable/Address Strobe:
This input is used to latch the address (present at the Microprocessor Interface
Address Bus, A[6:0]) into the Framer/UNI Microprocessor Interface circuitry and
to indicate the start of a READ or WRITE cycle. This input is active-"High" in the
Intel Mode (MOTO = “Low”) and active-”Low” in the Motorola Mode (MOTO =
“High”).
I
Chip Select Input:
This active-”Low” input signal selects the Microprocessor Interface Section of the
UNI/Framer and enables Read/Write operations between the “local” micropro-
cessor and the UNI/Framer on-chip registers and RAM locations.
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