XRT74L74 Datasheet, PDF (11/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 352
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)...................................................................................... 352
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)...................................................................................... 352
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 353
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ....................................................... 353
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) ........................................................ 353
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 354
TABLE 77: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE FRAMING STATE OF THE RE-
CEIVE E3 FRAMER BLOCK.................................................................................................................................................... 354
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 355
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)...................................................................................... 355
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 355
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)...................................................................................... 356
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 356
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 356
RXE3 CONFIGURATION & STATUS REGISTER - 1 G.751 (ADDRESS = 0X10)................................................................ 357
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)...................................................................................... 357
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 357
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) .......................................................................... 358
FIGURE 145. THE LOCAL RECEIVE E3 FRAMER BLOCK, RECEIVING AN E3 FRAME FROM THE REMOTE TERMINAL WITH A CORRECT BIP-4 VALUE.
358
FIGURE 146. THE LOCAL RECEIVE E3 FRAMER BLOCK, TRANSMITTING AN E3 FRAME TO THE REMOTE TERMINAL WITH THE “A” BIT SET TO “0”
359
FIGURE 147. THE LOCAL RECEIVE E3 FRAMER BLOCK, RECEIVING AN E3 FRAME FROM THE REMOTE TERMINAL WITH AN INCORRECT BIP-4
VALUE................................................................................................................................................................................. 360
FIGURE 148. THE LOCAL RECEIVE E3 FRAMER BLOCK, TRANSMITTING AN E3 FRAME TO THE REMOTE TERMINAL WITH THE “A” BIT-FIELD SET
TO “1”................................................................................................................................................................................. 360
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)...................................................................................... 361
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ......................................................................... 361
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) .......................................................................... 361
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................................................ 361
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)...................................................................................... 362
6.3.3 THE RECEIVE HDLC CONTROLLER BLOCK ........................................................................................................ 362
FIGURE 149. LAPD MESSAGE FRAME FORMAT................................................................................................................................... 363
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18................................................................................................. 363
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .................................................................................................. 364
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .................................................................................................. 364
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .................................................................................................. 365
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .................................................................................................. 365
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .................................................................................................. 365
TABLE 78: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MESSAGE TYPE/SIZE ....... 366
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18................................................................................................. 366
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .................................................................................................. 366
FIGURE 150. FLOW CHART DEPICTING THE FUNCTIONALITY OF THE LAPD RECEIVER........................................................................... 367
6.3.4 THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE ..................................................................................... 367
FIGURE 151. THE RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ..................................................................................................... 367
FIGURE 152. HOW TO INTERFACE THE TERMINAL EQUIPMENT TO THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK FOR METHOD 1
368
TABLE 79: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK FOR METHOD
1 ........................................................................................................................................................................................ 369
TABLE 80: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXOHFRAME WAS LAST SAMPLED
"HIGH”) TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ........................................................ 369
FIGURE 153. THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE OVERHEAD OUTPUT INTERFACE FOR METHOD 1.................................. 370
TABLE 81: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK (METHOD 2)
371
FIGURE 154. HOW TO INTERFACE THE TERMINAL EQUIPMENT TO THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK FOR METHOD 2
371
TABLE 82: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME WAS LAST SAMPLED "HIGH") TO
THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ......................................................................... 372
FIGURE 155. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK (FOR METHOD
2)....................................................................................................................................................................................... 373
6.3.5 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE ........................................................................................ 373
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