XRT74L74 Datasheet, PDF (169/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
4.3.2.7
GFC Nibble Extraction—via the RxGFC
Serial Output Port
The first four bit-field of each cell header are the GFC
bits. The Receive Cell processor will output the con-
tents of the GFC Nibble-field for each cell that it re-
ceives, via the “GFC Nibble Field” serial output port.
The “Receive GFC Nibble-Field” serial output port
consists of the following pins.
• RxGFC
• RxGFCClk
• RxGFCMSB
The data is output via the RxGFC output pin. The or-
der of transmission, within a given cell, is with the
MSB first and in descending order until transmitting
the LSB bit. Afterwards, the “GFC Nibble-field” serial
output port will output the MSB for the GFC Nibble-
field of the next cell. This data is clocked out on the
rising edge of the RxGFCClk output signal. The RxG-
FCMSB output pin will be pulsed “high” each time the
MSB of the GFC Nibble field, for a given cell, is
present at the RxGFC input. Figure 34 presents an il-
lustration depicting the behavior of the RxGFC Serial
Output Port signals.
FIGURE 34. ILLUSTRATION OF THE BEHAVIOR OF THE RXGFC SERIAL OUTPUT PORT SIGNALS
RxGFCClk
RxGFCMSB
RxGFC
t47
t48
t49
t50
BIT 3
t51
BIT 2
BIT 1
t52
BIT 0
4.3.2.8 Receive Cell Processor Interrupts
The Receive Cell Processor will generate interrupts
upon
• HEC Errors
• OAM Cell received
• Loss of Cell Delineation
If one of these conditions occur, and if that particular
condition is enabled for interrupt generation, then
when the local µC/µP reads the UNI Interrupt Status
Register, as shown below, it should read ‘xx1xxxxxb’
(where the -b suffix denotes a binary expression, and
‘x’ denotes a “don’t care” value).
UNI Interrupt Status Register (Address = 05h)
BIT 7
RxDS3
Interrupt
Status
RO
x
BIT 6
RxPLCP
Interrupt
Status
RO
x
BIT 5
RxCP
Interrupt
Status
RO
1
BIT 4
RxUTOPIA
Interrupt
Status
RO
x
BIT 3
TxUTOPIA
Interrupt
Status
RO
x
BIT 2
TxCP
Interrupt
Status
RO
x
BIT 1
TxDS3
Interrupt
Status
RO
x
BIT 0
One Sec
Interrupt
Status
RUR
x
At this point, the local µC/µP will have determined that
the Receive Cell Processor block is the source of the
interrupt, and that the Interrupt Service Routine
should branch accordingly. In order to accomplish this
the local µC/µP should now read the “RxCP Interrupt
Status Register” (Address = 4Fh). The bit format of this
register is presented below.
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