XRT74L74 Datasheet, PDF (10/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
FIGURE 125. FLOW CHART DEPICTING HOW TO USE THE LAPD TRANSMITTER..................................................................................... 328
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................................................... 329
6.2.4 THE TRANSMIT E3 FRAMER BLOCK..................................................................................................................... 330
FIGURE 126. THE TRANSMIT E3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO OTHER FUNCTIONAL BLOCKS ................................... 331
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................................................ 331
TABLE 70: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3 CONFIGURATION REGISTER, AND THE
RESULTING TRANSMIT E3 FRAMER BLOCK’S ACTION ............................................................................................................ 332
TABLE 71: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION REGISTER, AND THE RESULTING
TRANSMIT E3 FRAMER BLOCK’S ACTION.............................................................................................................................. 332
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................................................ 332
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35) .................................................................................................... 333
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................................................ 333
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ................................................................................................ 334
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48) ....................................................................................... 334
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49) ....................................................................................... 334
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A) .......................................................................................... 335
6.2.5 THE TRANSMIT E3 LINE INTERFACE BLOCK ...................................................................................................... 335
FIGURE 127. APPROACH TO INTERFACING THE XRT74L74 FRAMER IC TO THE XRT73L00 DS3/E3/STS-1 LIU .................................. 335
FIGURE 128. THE TRANSMIT E3 LIU INTERFACE BLOCK ...................................................................................................................... 336
FIGURE 129. THE BEHAVIOR OF TXPOS AND TXNEG SIGNALS DURING DATA TRANSMISSION WHILE THE TRANSMIT DS3 LIU INTERFACE IS OP-
ERATING IN THE UNIPOLAR MODE ........................................................................................................................................ 336
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 337
TABLE 72: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O CONTROL REGISTER AND THE
TRANSMIT E3 FRAMER LINE INTERFACE OUTPUT MODE ....................................................................................................... 337
FIGURE 130. AMI LINE CODE ............................................................................................................................................................. 338
FIGURE 131. TWO EXAMPLES OF HDB3 ENCODING............................................................................................................................. 338
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 339
TABLE 73: THE RELATIONSHIP BETWEEN BIT 4 (AMI/HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR LINE CODE THAT IS OUTPUT
BY THE TRANSMIT E3 LIU INTERFACE BLOCK....................................................................................................................... 339
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................................. 339
TABLE 74: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE TXLINECLK
CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ................................................................................................... 339
FIGURE 132. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG ARE CONFIGURED TO BE
UPDATED ON THE RISING EDGE OF TXLINECLK ..................................................................................................................... 340
FIGURE 133. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG ARE CONFIGURED TO BE
UPDATED ON THE FALLING EDGE OF TXLINECLK ................................................................................................................... 340
6.2.6 TRANSMIT SECTION INTERRUPT PROCESSING ................................................................................................. 340
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................................................... 341
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .......................................................................... 341
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .......................................................................... 342
6.3 THE RECEIVE SECTION OF THE XRT74L74 (E3 MODE OPERATION) ................................................... 342
FIGURE 134. THE RECEIVE SECTION OF THE XRT74L74 CONFIGURED TO OPERATE IN THE E3 MODE .................................................. 342
6.3.1 THE RECEIVE E3 LIU INTERFACE BLOCK ........................................................................................................... 342
FIGURE 135. THE RECEIVE E3 LIU INTERFACE BLOCK ........................................................................................................................ 343
FIGURE 136. BEHAVIOR OF THE RXPOS, RXNEG AND RXLINECLK SIGNALS DURING DATA RECEPTION OF UNIPOLAR DATA .................. 343
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 344
TABLE 75: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE TXLINECLK
CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ................................................................................................... 344
FIGURE 137. ILLUSTRATION ON HOW A CHANNEL OF THE RECEIVE E3 FRAMER (WITHIN THE XRT74L74 FRAMER IC) BEING INTERFACE TO
THEXRT73L00 LINE INTERFACE UNIT, WHILE OPERATING IN BIPOLAR MODE......................................................................... 345
FIGURE 138. AMI LINE CODE ............................................................................................................................................................. 346
FIGURE 139. TWO EXAMPLES OF HDB3 DECODING............................................................................................................................. 346
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................................. 347
TABLE 76: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE SAMPLING EDGE
OF THE RXLINECLK SIGNAL ................................................................................................................................................. 347
FIGURE 140. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND RXNEG ARE TO BE SAM-
PLED ON THE RISING EDGE OF RXLINECLK ........................................................................................................................... 348
FIGURE 141. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND RXNEG ARE TO BE SAM-
PLED ON THE FALLING EDGE OF RXLINECLK ......................................................................................................................... 348
6.3.2 THE RECEIVE E3 FRAMER BLOCK ....................................................................................................................... 348
FIGURE 142. THE RECEIVE E3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO THE OTHER FUNCTIONAL BLOCKS ............................. 349
FIGURE 143. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER E3 FRAME ACQUISITION/MAINTENANCE ALGORITHM ......... 350
FIGURE 144. THE E3, ITU-T G.751 FRAMING FORMAT ....................................................................................................................... 350
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 351
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