XRT74L74 Datasheet, PDF (4/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
ING. .................................................................................................................................................................................... 110
FIGURE 13. FLOW-CHART OF THE “UNI DEVICE SELECTION AND WRITE PROCEDURE” FOR THE MULTI-PHY OPERATION. ..................... 111
FIGURE 14. TIMING DIAGRAM OF THE TRANSMIT UTOPIA DATA AND ADDRESS BUS SIGNALS, DURING THE “MULTI-PHY” UNI DEVICE SELECTION
AND WRITE OPERATIONS..................................................................................................................................................... 111
3.2 TRANSMIT CELL PROCESSOR .................................................................................................................. 115
3.2.1 BRIEF DESCRIPTION OF THE TRANSMIT CELL PROCESSOR .......................................................................... 115
3.2.2 FUNCTIONAL DESCRIPTION OF TRANSMIT CELL PROCESSOR ...................................................................... 115
FIGURE 15. SIMPLE ILLUSTRATION OF THE TRANSMIT CELL PROCESSOR BLOCK AND THE ASSOCIATED EXTERNAL PINS........................ 115
FIGURE 16. FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT CELL PROCESSOR BLOCK ...................................................................... 116
FIGURE 17. BEHAVIOR OF TXGFC, TXGFCCLK, AND TXGFCMSB DURING GFC INSERTION INTO THE “OUTBOUND” CELL .................... 120
3.3 TRANSMIT PLCP PROCESSOR .................................................................................................................. 124
3.3.1 BRIEF DESCRIPTION OF THE TRANSMIT PLCP PROCESSOR .......................................................................... 124
3.3.2 DESCRIPTION OF THE PLCP FRAME AND THE PATH OVERHEAD (POH) BYTES........................................... 125
FIGURE 18. SIMPLE ILLUSTRATION OF THE TRANSMIT PLCP PROCESSOR BLOCK................................................................................. 125
3.3.3 FUNCTIONAL DESCRIPTION OF THE TRANSMIT PLCP PROCESSOR BLOCK ................................................ 127
FIGURE 19. FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT PLCP PROCESSOR ................................................................................ 127
FIGURE 20. AN ILLUSTRATION OF THE BEHAVIOR OF THE TXPOH SERIAL INTERFACE SIGNALS DURING USER INPUT OF POH DATA....... 134
3.4 TRANSMIT DS3 FRAMER ............................................................................................................................ 135
3.4.1 BRIEF DESCRIPTION OF THE TRANSMIT DS3 FRAMER .................................................................................... 135
3.5 TRANSMIT E3 FRAMER .............................................................................................................................. 135
3.5.1 BRIEF DESCRIPTION OF THE TANSMIT E3 FRAMER.......................................................................................... 135
4.0 THE RECEIVE SECTION ...................................................................................................................136
4.1 RECEIVE DS3 FRAMER ............................................................................................................................... 136
4.1.1 BRIEF DESCRIPTION OF THE RECEIVE DS3 FRAMER ....................................................................................... 136
FIGURE 21. BLOCK DIAGRAM OF THE RECEIVER DS3 FRAMER, WITH ASSOCIATED PINS........................................................................ 137
FIGURE 22. FUNCTIONAL BLOCK DIAGRAM OF RECEIVER FRAMER ....................................................................................................... 138
4.2 RECEIVE PLCP PROCESSOR .................................................................................................................... 138
4.2.1 OPERATION OF THE RECEIVE PLCP PROCESSOR ............................................................................................ 138
FIGURE 23. ILLUSTRATION OF THE SIMPLE BLOCK DIAGRAM OF THE RECEIVE PLCP PROCESSOR ........................................................ 139
4.2.2 FUNCTIONAL DESCRIPTION OF THE RECEIVE PLCP PROCESSOR ................................................................ 139
FIGURE 24. FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE PLCP PROCESSOR BLOCK....................................................................... 139
FIGURE 25. STATE MACHINE DIAGRAM OF THE RECEIVE PLCP PROCESSOR FRAMING ALGORITHM ...................................................... 141
FIGURE 26. TIMING RELATIONSHIP BETWEEN THE RECEIVE PLCP POH BYTE SERIAL OUTPUT PORT PINS—RXPOH, RXPOHFRAME AND RX-
POHCLK. ........................................................................................................................................................................... 146
4.3 RECEIVE CELL PROCESSOR ..................................................................................................................... 148
4.3.1 BRIEF DESCRIPTION OF THE RECEIVE CELL PROCESSOR ............................................................................. 148
FIGURE 27. SIMPLE ILLUSTRATION OF THE RECEIVE CELL PROCESSOR, WITH ASSOCIATED PINS........................................................... 148
4.3.2 FUNCTIONAL DESCRIPTION OF RECEIVE CELL PROCESSOR ......................................................................... 148
FIGURE 28. FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE CELL PROCESSOR.................................................................................... 149
FIGURE 29. CELL DELINEATION ALGORITHM EMPLOYED BY THE RECEIVE CELL PROCESSOR, WHEN THE UNI IS OPERATING IN THE “DIRECT-
MAPPED” ATM MODE. ........................................................................................................................................................ 150
FIGURE 30. ILLUSTRATION OF OVERALL CELL FILTERING/PROCESSING PROCEDURING THE OCCURS WITHIN THE RECEIVE CELL PROCESSOR
152
FIGURE 31. STATE MACHINE DIAGRAM OF THE HEC BYTE ERROR CORRECTION/DETECTION ALGORITHM............................................. 153
FIGURE 32. AN APPROACH TO PROCESSING SEGMENT OAM CELLS, VIA THE RECEIVE CELL PROCESSOR. ........................................... 164
FIGURE 33. APPROACH TO PROCESSING “END-TO-END” OAM CELLS .................................................................................................. 164
FIGURE 34. ILLUSTRATION OF THE BEHAVIOR OF THE RXGFC SERIAL OUTPUT PORT SIGNALS ............................................................. 167
4.4 RECEIVE UTOPIA INTERFACE BLOCK ..................................................................................................... 168
4.4.1 BRIEF DESCRIPTION OF THE RECEIVE UTOPIA INTERFACE BLOCK.............................................................. 168
4.4.2 FUNCTIONAL DESCRIPTION OF RECEIVE UTOPIA............................................................................................. 168
FIGURE 35. SIMPLE BLOCK DIAGRAM OF RECEIVE UTOPIA BLOCK OF UNI. ........................................................................................ 168
FIGURE 36. FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE UTOPIA INTERFACE BLOCK ..................................................................... 170
FIGURE 37. TIMING DIAGRAM OF RXUCLAV/RXEMPTYB AND VARIOUS OTHER SIGNALS DURING READS FROM THE RECEIVE UTOPIA, WHILE OP-
ERATING IN THE OCTET-LEVEL HANDSHAKING MODE. ........................................................................................................... 174
FIGURE 38. TIMING DIAGRAM OF VARIOUS RECEIVE UTOPIA INTERFACE BLOCK SIGNALS, WHEN THE RECEIVE UTOPIA INTERFACE BLOCK IS
OPERATING IN THE “CELL LEVEL” HANDSHAKE MODE ........................................................................................................... 175
FIGURE 39. SIMPLE ILLUSTRATION OF SINGLE-PHY OPERATION .......................................................................................................... 178
FIGURE 40. FLOW CHART DEPICTING THE APPROACH THAT THE ATM LAYER PROCESSOR SHOULD TAKE WHEN READING CELL DATA FROM THE
RECEIVE UTOPIA INTERFACE, IN THE SINGLE-PHY MODE................................................................................................... 179
FIGURE 41. TIMING DIAGRAM OF ATM LAYER PROCESSOR RECEIVING DATA FROM THE UNI OVER THE UTOPIA DATA BUS, (SINGLE-PHY
MODE/CELL LEVEL HANDSHAKING). ..................................................................................................................................... 180
FIGURE 42. TIMING DIAGRAM OF ATM LAYER PROCESSOR RECEIVING DATA FROM THE UNI OVER THE UTOPIA DATA BUS, (SINGLE-PHY
MODE/OCTET LEVEL HANDSHAKING). .................................................................................................................................. 180
FIGURE 43. AN ILLUSTRATION OF MULTI-PHY OPERATION WITH UNI DEVICES #1 AND #2 .................................................................... 182
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