XRT74L74 Datasheet, PDF (12/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
FIGURE 156. THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK............................................................................................... 373
TABLE 83: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK............. 374
FIGURE 157. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74
FRAMER IC (SERIAL MODE OPERATION) .............................................................................................................................. 375
FIGURE 158. AN ILLUSTRATION OF THE BEHAVIOR OF THE SIGNALS BETWEEN THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK OF THE
XRT74L74 AND THE TERMINAL EQUIPMENT......................................................................................................................... 376
FIGURE 159. THE XRT74L74 DS3/E3 FRAMER IC BEING INTERFACED TO THE RECEIVE SECTION OF THE TERMINAL EQUIPMENT (NIBBLE-PAR-
ALLEL MODE OPERATION).................................................................................................................................................... 377
FIGURE 160. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK (FOR NIBBLE-
PARALLEL MODE OPERATION). ............................................................................................................................................ 378
6.3.6 RECEIVE SECTION INTERRUPT PROCESSING.................................................................................................... 378
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................................................... 379
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ...................................................................................... 379
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 380
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)........................................................................... 380
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ...................................................................................... 381
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 381
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 381
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ...................................................................................... 382
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)........................................................................... 382
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ...................................................................................... 383
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)........................................................................... 383
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12).................................................................................... 384
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 384
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ...................................................................................... 385
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ...................................................................................... 385
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)........................................................................... 385
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ...................................................................................... 386
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ...................................................................................... 386
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ...................................................................................... 387
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ...................................................................................... 387
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)................................................................................................ 387
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)................................................................................................ 388
7.0 E3/ITU-T G.832 OPERATION OF THE XRT74L74 ............................................................................389
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 389
7.1 DESCRIPTION OF THE E3, ITU-T G.832 FRAMES AND ASSOCIATED OVERHEAD BYTES ................. 389
FIGURE 161. E3, ITU-T G.832 FRAMING FORMAT. ............................................................................................................................. 389
7.1.1 DEFINITION OF THE OVERHEAD BYTES .............................................................................................................. 389
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 390
TABLE 84: DEFINITION OF THE TRAIL TRACE BUFFER BYTES, WITHIN THE E3, ITU-T G.832 FRAMING FORMAT .................................... 390
THE MAINTENANCE AND ADAPTATION (MA) BYTE FORMAT............................................................................................ 391
TABLE 85: VARIOUS PAYLOAD TYPE VALUES AND THEIR CORRESPONDING MEANING ............................................................................ 392
7.2 THE TRANSMIT SECTION OF THE XRT74L74 (E3 MODE OPERATION) ................................................ 392
FIGURE 162. THE TRANSMIT SECTION WHEN IT HAS BEEN CONFIGURED TO OPERATE IN THE E3 MODE ................................................. 393
7.2.1 THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........................................................................... 393
FIGURE 163. THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ................................................................................................ 393
TABLE 86: PIN LIST AND DESCRIPTIONS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE ....................................... 394
FIGURE 164. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74
FOR MODE 1 (SERIAL/LOOP-TIMED) OPERATION .................................................................................................................. 396
FIGURE 165. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE
XRT74L74 AND THE TERMINAL EQUIPMENT (FOR MODE 1 OPERATION) ............................................................................... 397
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 397
FIGURE 166. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74
FOR MODE 2 (SERIAL/LOCAL-TIMED/FRAME-SLAVE) OPERATION .......................................................................................... 398
FIGURE 167. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (MODE 2 OPERATION)
399
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 399
FIGURE 168. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74
FOR MODE 3 (SERIAL/LOCAL-TIMED/FRAME-MASTER) OPERATION ....................................................................................... 400
FIGURE 169. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (E3 MODE 3 OPER-
ATION) ................................................................................................................................................................................ 401
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 401
X