XRT74L74 Datasheet, PDF (120/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
TABLE 8: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT-FIELD 5 (HEC INSERT ENABLE) WITHIN THE TXCP
CONTROL REGISTER, AND THE HEC BYTE CALCULATOR’S HANDLING OF VALID CELLS
HEC INSERT ENABLE
RESULT
1
The HEC Byte is calculated and is inserted into the 5th octet position of each valid cell.
Upon power up or reset, the “HEC Byte Calculator
and Insertion” feature is enabled. A “0” must be writ-
ten to this bit in order to disable this operation.
TxCP Control Register (Address = 60h)
BIT 7
BIT 6
BIT 5
BIT 4
Scrambler
En
Coset
Enable
HEC Insert
Enable
TDPChk
Pattern
R/W
R/W
R/W
R/W
1
1
1
1
3.2.2.1.2 Configuring the “HEC Byte Calculator
and Insertion” Feature for Idle Cells
The “HEC Byte Calculation and Insertion” feature can
be separately enabled or disabled for the outbound Idle
Cells. This option is exercised by writing the appropri-
ate value to bit 1 (Idle Cell HEC CalEn) within the Tx-
CP Control Register, as depicted below.
BIT 3
GFC Insert
Enable
R/W
0
BIT 2
TDPErr
Interrupt
Enable
R/W
0
BIT 1
Idle Cell
HEC
CalEn
R/W
x
BIT 0
TDPErr
Interrupt
Status
RUR
0
This “Read/Write” bit-field is used for enabling or dis-
abling the “Calculation and Insertion” of the HEC byte
into the Idle Cell as illustrated below. If disabling this
feature is chosen, then the 5th octet of the Idle Cells
will be transmitted to the Transmit PLCP (or Transmit
DS3 Framer) block as programmed in the “TxCP Idle
Cell Pattern Header—Byte 5” register (Address =
68h).
TABLE 9: THE RELATIONSHIP BETWEEN THE CONTENTS WITHIN BIT 1 (IC HEC CALC EN) OF THE “TXCP CONTROL
REGISTER” AND THE RESULTING HANDLING OF IDLE CELLS, BY THE “HEC BYTE CALCULATOR”
IC HEC CALC EN
0
1
RESULT
The entire programmed Idle Cell header is transmitted without Modification
The HEC byte is calculated, via the first four bytes of the header, and is inserted into the fifth octet
position within each Idle Cell.
Upon power up or reset, the Transmit Cell Processor
will be configured such that the HEC bytes will be cal-
culated and inserted into the fifth octet position of
each Idle Cell. A “0” must be written to this bit-field in
order to disable this feature.
3.2.2.1.3 Modulo-2 Addition of Coset
Polynomial to the HEC Byte Value
When enabled, the HEC Byte Calculator takes the
first four bytes of each cell and computes a CRC-8
value via the generating polynomial x⁸ + x² + x + 1.
The BISDN Physical Layer specifications (ITU
Recommendations I.432) specifies that this CRC-8 (or
HEC) value can optionally be modulo-2 added to the
polynomial x⁶ + x⁴ + x² + 1; and inserting the result of
this calculation into the fifth byte of each cell. The pur-
pose of this option is to provide protection against bit
slips. This protection is not required in transmission
systems that ensure adequate one’s density. Howev-
er, this operation does provide protection against all ze-
ros cells that could be passed to the ATM Layer during
a loss of signal condition on the transmission medium.
The ATM Forum UNI specifications also requires this
operation.
This modulo-2 addition can be enabled or disabled by
writing the appropriate value to bit 6 (Coset Enable)
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