XRT74L74 Datasheet, PDF (182/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
FIGURE 41. TIMING DIAGRAM OF ATM LAYER PROCESSOR RECEIVING DATA FROM THE UNI OVER THE UTOPIA
DATA BUS, (SINGLE-PHY MODE/CELL LEVEL HANDSHAKING).
1
2
3
4
5
6
7
8
9
31
32
34
RxUClk
RxUClav
RxUEn
RxUData [15:0] W24 W25
RxUSoC
W26
W0
W1 W2
W25 W26
Note: regarding Figure 41
1. The Receive UTOPIA Data bus is configured to be
16 bits wide. Hence, the data, which the Receive
UTOPIA Interface block places on the Receive
UTOPIA Data bus, is expressed in terms of 16-bit
words: (e.g., W0–W26).
2. The Receive UTOPIA Data bus is configured to
handle 54 bytes/cell. Hence, Figure 41 illustrates
the ATM Layer processor reading 27 words (W0
through W26) for each ATM cell.
3. The Receive UTOPIA Interface block is configured
to operate in the Cell Level Handshake mode.
FIGURE 42. TIMING DIAGRAM OF ATM LAYER PROCESSOR RECEIVING DATA FROM THE UNI OVER THE UTOPIA
DATA BUS, (SINGLE-PHY MODE/OCTET LEVEL HANDSHAKING).
1
2
3
4
5
6
7
8
9
10
11
12
RxUClk
RxUClav
RxUEn
RxUData [15:0]
W0 W1
X
W2 W3
W4
RxUSoC
Note: regarding Figure 42
1. The Receive UTOPIA Data bus is configured to be
16 bits wide. Hence, the data, which the ATM Layer
processor places on the Transmit UTOPIA Data
bus, is expressed in terms of 16 bit words: (e.g.,
W0–W26).
2. The Receive UTOPIA Interface block is configured
to handle 54 bytes/cell. Hence, Figure 42 illus-
trates the ATM Layer processor reading 27 words
(W0 through W26) for each ATM cell.
3. The Receive UTOPIA Interface block is configured
to operate in the Octet-Level Handshaking Mode.
Final Comments on Single-PHY Mode
The RxUClav pin exhibits a role that is similar to the
“Ready Ready” function in RS-232 based data com-
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