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XRT74L74 Datasheet, PDF (157/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER | |||
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PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
The âDetectionâ State
When the âHEC Byte Error Detection/Correctionâ
algorithm is operating in the Detection mode, then
all errored cells (e.g., those cells with single-bit errors
and multi-bit errors) will be discarded, unless config-
ured otherwise. To configure the Receive Cell Pro-
cessor to retain errored cells, write to bit 0 (HEC Error
Ignore) of the RxCP Configuration register (Address
= 4Ch), as described above.
The âHEC Byte Error Correction/Detectionâ Algorithm
will transition back into the âCorrectionâ state once the
Receive Cell Processor has detected âMâ consecutive
cells with the correct HEC byte values. The user has
the option to use the following values for âMâ: 0, 1, 3,
and 7. To configure the UNI to use any of these val-
ues for M, write the appropriate values to the âRxCP
Additional Configurationâ Register (Address = 4Dh),
as depicted below.
RxCP Additional Configuration Register (Address = 4Dh)
BIT 7
BIT 6
Unused
RO
RO
BIT 5
User Cell Filter
Discard
R/W
BIT 4
User Cell Filter
Enable
R/W
BIT 3
BIT 2
Correction Threshold [1, 0]
R/W
R/W
BIT 1
Correct
Enable
R/W
BIT 0
Unused
RO
The definition of the bits relevant to the âHEC Byte Er- out of the âCorrectionâ as dictated by the âCorrection
ror Correction/Detectionâ algorithm follow:
Thresholdâ.
Bit 1âCorrection (Mode) Enable
This âRead/Writeâ bit field is used to enable/disable
the âCorrection Modeâ portion of the âHEC Byte Error
Correction/Detectionâ algorithm. If a â0â is written to
this bit-field, the âHEC Byte Error Correction/Detectionâ
algorithm will be disabled from entry/operation in the
âCorrectionâ mode. Therefore, the Receive Cell Pro-
cessor will only operate in the âDetectionâ mode. If a
â1â is written to this bit field then the âHEC Byte Error
Correction/Detectionâ algorithm will transition into and
Bits 2 and 3âCorrection Threshold [1, 0]
These âRead/Writeâ bit-fields are used to select the
âCorrectionâ Threshold for the âHEC Byte Error Cor-
rection/Detectionâ algorithm. The following table re-
lates the content of these bit-fields to the Correction
Threshold Value (M). Once again, M is the number of
consecutive âError-Freeâ cells that the Receive Cell
Processor must detect before the âHEC Byte Correc-
tion/Detectionâ algorithm will allow a transition back
into the âCorrectionâ Mode.
TABLE 24: THE RELATIONSHIP BETWEEN CORRTHRESHOLD[1:0] AND THE âCORRECTION THRESHOLDâ VALUE (M)
BIT 3
0
0
1
1
BIT 2
0
1
0
1
CORRECTION THRESHOLD VALUE (M)
M=0
M=1
M=3
M=7
4.3.2.3 Cell Filtering
As mentioned earlier, the Receive Cell Processor will fil-
ter (e.g., discard) incoming cells based upon the follow-
ing criteria.
⢠HEC Byte Errors (via the âHEC Byte Correction/
Detectionâ algorithm, as described in 7.3.2.2.)
⢠Idle Cells
⢠Header Byte PatternsâUser Cells
⢠Segment OAM Cells
Each of these cell filtering approaches are presented
below.
Filtering of Cells with HEC Byte Errors
Please see the âHEC Byte Correction/Detectionâ
algorithm in Section 7.3.2.2.
4.3.2.3.1 Idle Cell Filtering
The Receive Cell Processor can be configured to ei-
ther discard or retain Idle cells by writing to bit 4 (Idle
Cell Discard) of the RxCP Configuration Register, as
depicted below.
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