XRT74L74 Datasheet, PDF (7/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04).......................................................................................... 242
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31)....................................................... 242
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31)....................................................... 243
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ....................................................................... 243
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ....................................................................... 244
5.3 THE RECEIVE SECTION OF THE XRT74L74 (DS3 MODE OPERATION) ................................................ 244
FIGURE 79. A SIMPLE ILLUSTRATION OF THE RECEIVE SECTION OF THE XRT74L74, WHEN IT HAS BEEN CONFIGURED TO OPERATE IN THE DS3
MODE................................................................................................................................................................................. 244
5.3.1 THE RECEIVE DS3 LIU INTERFACE BLOCK......................................................................................................... 244
FIGURE 80. A SIMPLE ILLUSTRATION OF THE RECEIVE DS3 LIU INTERFACE BLOCK ............................................................................. 245
FIGURE 81. BEHAVIOR OF THE RXPOS, RXNEG AND RXLINECLK SIGNALS DURING DATA RECEPTION OF UNIPOLAR DATA .................... 245
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 246
TABLE 51: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE I/O CONTROL REGISTER AND THE TXLI-
NECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON........................................................................................ 246
FIGURE 82. ILLUSTRATION ON HOW THE RECEIVE DS3 FRAMER (WITHIN THE XRT74L74 FRAMER IC) BEING INTERFACED TO THEXRT73L00
LIU, WHILE THE FRAMER IS OPERATING IN BIPOLAR MODE (ONE CHANNEL SHOWN) ............................................................... 246
FIGURE 83. ILLUSTRATION OF AMI LINE CODE .................................................................................................................................... 247
FIGURE 84. ILLUSTRATION OF TWO EXAMPLES OF B3ZS DECODING ..................................................................................................... 248
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................................. 248
TABLE 52: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE SAMPLING EDGE
OF THE RXLINECLK SIGNAL ................................................................................................................................................. 249
FIGURE 85. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND RXNEG ARE TO BE SAMPLED
ON THE RISING EDGE OF RXLINECLK ................................................................................................................................... 249
FIGURE 86. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND RXNEG ARE TO BE SAMPLED
ON THE FALLING EDGE OF RXLINECLK ................................................................................................................................. 249
5.3.2 THE RECEIVE DS3 FRAMER BLOCK..................................................................................................................... 250
FIGURE 87. A SIMPLE ILLUSTRATION OF THE RECEIVE DS3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO THE OTHER FUNCTIONAL BLOCKS
250
FIGURE 88. THE STATE MACHINE DIAGRAM FOR THE RECEIVE DS3 FRAMER BLOCK’S FRAME ACQUISITION/MAINTENANCE ALGORITHM 251
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 252
TABLE 53: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (FRAMING ON PARITY) WITHIN THE RX DS3 CONFIGURATION AND STATUS
REGISTER, AND THE RESULTING FRAMING ACQUISITION CRITERIA......................................................................................... 252
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 252
TABLE 54: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RX DS3 CONFIGURATION AND STATUS REGISTER,
AND THE RESULTING F-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE DS3 FRAMER BLOCK................................... 253
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 253
TABLE 55: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE RX DS3 CONFIGURATION AND STATUS REGIS-
TER, AND THE RESULTING M-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE DS3 FRAMER BLOCK ......................... 253
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 253
I/O CONTROL REGISTER (ADDRESS = 0X01) .............................................................................................................. 254
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52) ..................................................... 254
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53) ...................................................... 254
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 255
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 255
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 256
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 256
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ....................................................................... 256
RX DS3 STATUS REGISTER (ADDRESS = 0X11) ......................................................................................................... 257
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................................... 257
RXDS3 STATUS REGISTER (ADDRESS = 0X11) .......................................................................................................... 258
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ........................................................................................ 258
PMON PARITY ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X54) .............................................................. 258
PMON PARITY ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X55) ............................................................... 258
FIGURE 89. A SIMPLE ILLUSTRATION OF THE LOCATIONS OF THE SOURCE, MID-NETWORK AND SINK TERMINAL EQUIPMENT (FOR CP-BIT PRO-
CESSING) ............................................................................................................................................................................ 259
FIGURE 90. ILLUSTRATION OF THE PRESUMED CONFIGURATION OF THE MID-NETWORK TERMINAL EQUIPMENT ..................................... 260
5.3.3 THE RECEIVE HDLC CONTROLLER BLOCK ........................................................................................................ 261
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................................ 262
RX DS3 FEAC REGISTER (ADDRESS = 0X16) ........................................................................................................... 262
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................................ 262
FIGURE 91. FLOW DIAGRAM DEPICTING HOW THE RECEIVE FEAC PROCESSOR FUNCTIONS ................................................................. 263
FIGURE 92. LAPD MESSAGE FRAME FORMAT..................................................................................................................................... 264
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