XRT74L74 Datasheet, PDF (312/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
The Terminal Equipment will serially output the data
on the E3_Data_Out[3:0] pins, upon the rising edge
of the signal at the E3_Clock_In input pin.
NOTE: The E3_Data_Out[3:0] output pins of the Terminal
Equipment is electrically connected to the TxNib[3:0] input
pins.
The XRT74L74 will latch the data, residing on the Tx-
Nib[3:0] input pins, on the rising edge of the TxNibClk
signal.
In this case, the Terminal Equipment has the respon-
sibility of providing the framing reference signal by
pulsing the Tx_Start_of_Frame output pin (and in
turn, the TxFrameRef input pin of the XRT74L74)
"High" for one bit-period, coincident with the first bit of
a new E3 frame. Once the XRT74L74 detects the ris-
ing edge of the input at its TxFrameRef input pin, it
will begin generation of a new E3 frame.
Finally, the XRT74L74 will always internally generate
the Overhead bits, when it is operating in both the E3
and Nibble-parallel modes. The XRT74L74 will pull
the TxOHInd input pin "Low".
The behavior of the signals between the XRT74L74
and the Terminal Equipment for E3 Mode 5 Operation
is illustrated in Figure 116 .
FIGURE 116. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL
EQUIPMENT (E3, MODE 5 OPERATION)
Terminal Equipment Signals
TxInClk
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
Payload Nibble [380]
Overhead Nibble [0]
XRT74L74 Transmit Payload Data I/F Signals
TxInClk
TxNibClk
TxNib[3:0]
TxFrameRef
Nibble [380]
Overhead Nibble [0]
TxOH_Ind
Note: Terminal Equipment pulses
“TxFrameRef” in order to denote
the E3 Frame Boundary.
E3 Frame Number N
E3 Frame Number N + 1
TxOH_Ind pulses high for 3 Nibble periods
How to configure the XRT74L74 into Mode 5
1. Set the NibIntf input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "01" as illus-
trated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
Local
Loopback
BIT 6
DS3/E3*
R/W
R/W
BIT 5
Internal
LOS
Enable
R/W
BIT 4
RESET
R/W
BIT 3
Interrupt
Enable
Reset
R/W
BIT2
Frame
Format
R/W
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
310