XRT74L74 Datasheet, PDF (314/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
In Figure 117 both the Terminal Equipment and the
XRT74L74 will be driven by an external 8.592MHz
clock signal. The Terminal Equipment will receive the
8.592MHz clock signal via the E3_Nib_Clock_In input
pin. The XRT74L74 will output the 8.592MHz clock
signal via the TxNibClk output pin.
The Terminal Equipment will serially output the data
on the E3_Data_Out[3:0] pins upon the rising edge of
the signal at the E3_Clock_In input pin. The
XRT74L74 will latch the data, residing on the Tx-
Nib[3:0] input pins, on the rising edge of the TxNibClk
signal.
In this case the XRT74L74 has the responsibility of
providing the framing reference signal by pulsing the
TxFrame output pin (and in turn the
Tx_Start_of_Frame input pin of the Terminal Equip-
ment) "High" for one bit-period, coincident with the
last bit within a given E3 frame.
Finally, the XRT74L74 will always internally generate
the Overhead bits, when it is operating in both the E3
and Nibble-parallel modes. The XRT74L74 will pull
the TxOHInd input pin "Low".
The behavior of the signals between the XRT74L74
and the Terminal Equipment for E3 Mode 6 Operation
is illustrated in Figure 118 .
FIGURE 118. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL
EQUIPMENT (E3 MODE 6 OPERATION)
Terminal Equipment Signals
TxInClk
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
Payload Nibble [380]
Overhead Nibble [0]
XRT74L74 Transmit Payload Data I/F Signals
TxInClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [380]
Overhead Nibble [0]
TxOH_Ind
Note: TxNibFrame pulses high to denote
E3 Frame Boundary.
E3 Frame Number N
E3 Frame Number N + 1
TxOH_Ind pulses high for 3 Nibble periods
How to configure the XRT74L74 into Mode 6
1. Set the NibInt input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "1X" as
illustrated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
Local
Loopback
BIT 6
DS3/E3*
BIT 5
Internal
LOS
Enable
BIT 4
RESET
BIT 3
Interrupt
Enable
Reset
BIT2
Frame
Format
BIT 1
BIT 0
TimRefSel[1:0]
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