S6J3200 Datasheet, PDF (91/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4 AC Characteristics
8.4.1 Source Clock Timing
(Condition: See 8.2. Operation Assurance )
Parameter
Symbol
Pin
Name
Conditions
Value
Min Typ Max
Unit
Remarks
Source oscillation
FC
X0, X1
-
3.6
-
16 MHz
clock frequency
Source oscillation
clock cycle time
tCYL
X0, X1
-
250.0 - 277.8 ns
CAN PLL jitter
(when locked)
tPJ
-
-
-10
-
10
ns
Internal Slow CR
FCRS
-
oscillation frequency
-
50 100 150 kHz
Internal Fast CR
FCRF
-
oscillation frequency
-
2.40 4.00 5.61- MHz
Before
trim
3.20 4.00 4.81 MHz After trim
Notes:
− The maximum/minimum values have been standardized with the main clock and PLL clock in use.
− The error of source oscillator frequency must be smaller than 3000ppm.
− Enough evaluation and adjustment are recommended using oscillator on your system board.
− X0 and X1 clock timing
tCYL
X0
CAN PLL jitter
A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles.
Ideal clock
Slow
PLL output
Fast
Document Number: 002-05682 Rev.*A
Page 91 of 179