S6J3200 Datasheet, PDF (157/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
Summary
Error
Correct
ID
Vcc12 power
62
supply
Current
69
consumption
Vcc5 current
69
consumption
Current
consumption of 69
FPD link
Source clock error 72
Vss12:
62
1.15(min), 1.3(max)
ICC12: -(typ), 1900(max)
ICCT5: -(typ), 2620(max)
68
ICCH5: -(typ), 2620(max)
ICC5 Normal operation 60mA(max)
68
-
68
Note:
- ,,,,
71
- Jitter of source oscillator must be smaller
than 300ppm.
Vss12:
1.15(min), 1.3(max)
1.1(min)*1, 1.3(max)
− *1. The value will be for the product
series with revision digit B.
#169
ICC12: 950(typ),1900(max)
ICCT5: 350(typ),700(max)
ICCH5: 150(typ),450(max)
#170
ICC5 Normal operation 45mA(typ),
75mA(max)
#181
ILVDS:
VCC3_LVDS_Tx,AVCC3_LVDS_PLL: #204
70mA (FPD-Link)
Note:
- ,,,,
#178
- The error of source oscillator frequency
must be smaller than 300ppm.
Trace clock
74, 75 FCLK_TRC: 50MHz
73, 74
FCLK_TRC: 100MHzNote;- FCLK_TRC/2
(half frequency of FCLK_TRC) comes out
#182
of the trace clock port of package external
pin.
Notes;
-,,,
- Even if a combination of clock frequency
is able to be configured by software, the
frequency should be configured under
maximum frequency described in Table.
For example, 80MHz of CLK_LCP0A
Internal clock
Notes;
75
frequency
-,,,
seems to be configurable from both
74
divided 240MHz and 160MHz of
#180
CLK_CPU. But each duty ratio of
configured 80MHz as an internal signal is
different from one another. In this series,
the 80MHz from the 160MHz divided by 2
can only be assured, but the 240MHz
divided by 3 cannot be assured from the
internal timing design point of view.
Level detection voltage: 2.15(min)
Power On
condition
Level detection voltage: 2.25(min) 2.45(typ)
2.35(typ) 2.55(max)
79
78
#138
2.65(max)
Reset release voltage: 2.25(min) 2.45(typ)
2.65(max)
Document Number: 002-05682 Rev.*A
Page 157 of 179