S6J3200 Datasheet, PDF (165/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
Summary
Error
Correct
ID
Original document code: DS708-00003-0v04-E, Previous document code: DS708-00003-0v03-E
Rev. 1.0 June 30, 2015
TxCLK- LVDS clock output pin: Described
as TXOUT4M in FPD-Link Converter
TxCLK+ LVDS clock output pin:
Described as TXOUT4P in FPD-Link
Converter
TxDOUT0- LVDS data output pin:
Described as TXOUT0M in FPD-Link
Converter
TxDOUT0+ LVDS data output pin:
Described as TXOUT0P in FPD-Link
Converter
TxDOUT1- LVDS data output pin:
Described as TXOUT1M in FPD-Link
FPD-Link port
45
-
definition
60-61
Converter
TxDOUT1+ LVDS data output pin:
Described as TXOUT1P in FPD-Link
#146
Converter
TxDOUT2- LVDS data output pin:
Described as TXOUT2M in FPD-Link
Converter
TxDOUT2+ LVDS data output pin:
Described as TXOUT2P in FPD-Link
Converter
TxDOUT3- LVDS data output pin:
Described as TXOUT3M in FPD-Link
Converter
TxDOUT3+ LVDS data output pin:
Described as TXOUT3P in FPD-Link
Converter
Non support port 21, 23 -
25, 27,
28, 29, (Added the Note for non-supported pin
32, 34, condition on PCB)
35, 36
#215
Current
consumption of 70
FPD link
AVcc and AVRH
58
description
TEQFP256
11
support
VCC3_LVDS_Tx, AVCC3_LVDS_PLL: 70
92
mA(max)
(AVCC0, AVCC1, AVRH0, and AVRH1) 73
Pin count N:320
12
VCC3_LVDS_TX: 56mA(max)
AVCC3_LVDS_PLL: 7mA(max)
(AVCC,AVRH)
Pin count M:256
#246
#250
#272
Document Number: 002-05682 Rev.*A
Page 165 of 179