S6J3200 Datasheet, PDF (108/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
(4) SPI Supported (SCR:SPI=1), and Mark Level "L" of Serial Clock Output (SMR:SCINV=1)
Parameter
Serial clock
cycle time
SCK ↓ -> SOT
delay time
Valid SIN -> SCK ↑
setup time
SCK ↑ -> Valid SIN
hold time
SOT -> SCK ↑
delay time
Serial clock
"H" pulse width
Serial clock
"L" pulse width
SCK ↓ -> SOT
delay time
Symbol
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
tSHSL
tSLSH
tSLOVE
Pin Name
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0 to SIN4,
SIN8 to SIN12,
SIN16 to SIN17
SCK0 to SCK4,
SCK8 to SCK12
SOT0 to SOT4,
SOT8 to SOT12
SCK16 to SCK17
SOT16 to SOT17
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
Conditions
(Condition: See 8.2. Operation Assurance )
Value
Min
Max
Unit
Remarks
6tCLK_LCPnA*1
-
ns
3tCLK_COMP
-
ns
Master
-15
Mode
(CL = 50pF,
IOL=-2mA,
IOH=2mA),
20
(CL=20pF,
IOL=-1mA,
IOH=1mA)
0
+15
ns
-
ns
-
ns
tCLK_LCPnA*1
-15
-
ns
tCLK_COMP -15
-
ns
tCLK_LCPnA*1 -5
-
ns
tCLK_COMP -5
-
ns
Slave
Mode
(CL=50pF,
IOL=-2mA,
2tCLK_LCPnA*1
-5
-
ns
IOH=2mA),
(CL=20pF, 2tCLK_COMP -5
-
ns
IOL=-1mA,
IOH=1mA)
-
20
ns
Document Number: 002-05682 Rev.*A
Page 108 of 179