S6J3200 Datasheet, PDF (125/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4.12.2 Display Controller0 Timing (RSDS)
Parameter
Clock Cycle
Output delay from
DSP0_CLK↑
Output data valid
time
SP Output delay
from DSP0_CLK↑
SP high time
RSDS Transition
time
Rise and Fall
Symbol
tRSCYC
|tRSD|
tRSV
tSPD
tSPV
TRTF
Pin Name
DSP0_CLK+
DSP0_CLK-
DSP0_DATA_D11~0+
DSP0_DATA_D11~0-
DSP0_DATA_D11~0+
DSP0_DATA_D11~0-
DSP0_CTRL11~0
DSP0_CTRL11~0
DSP0_DATA_D11~0+
DSP0_DATA_D11~0-
Notes:
− For *1, the value can be configured and adjusted.
− For *2, SP high time can be configured.
Conditions
(CL = 20pF,
IOL=-4mA,
IOH=4mA)
20 to 80%
CL = 5pF,
VOD=200m
V
(Condition: See 8.2. Operation Assurance )
Value
Min
Max
Unit
Remarks
12.5
-
ns
-
7.3
ns
*1
tRSCYC/2-
1.6
-
ns
-
10.4
ns
tRSCYC
-
ns
*2
-
-
ps Typ : 500ps
t_RSCYC
DSP0_CLK+ V_OH
DSP0_CLK-
t_SPD
SP
V_OH
(DSP0_CTRL0~11)
V_OL
V_OH
t_SPV
V_OL
DSP0_DATA_D11~0+
DSP0_DATA_D11~0-
t_SPRS
V_OH
V_OL
V_OH
t_RSV
t_RSD
t_RSD
t_RSV
t_RSV
V_OH
valid
valid
V_OL
Document Number: 002-05682 Rev.*A
Page 125 of 179