S6J3200 Datasheet, PDF (75/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
WARNING:
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Notes:
− TA: Ambient temperature (JEDEC)
− TC: Case temperature (JEDEC), the maximum measured temperature of package case top.
− Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature.
− The following condition should be satisfied in order to facilitate heat dissipation.
1. 4 or more layers PCB should be used.
2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (JEDEC
standard)
3. 1 layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90% or
more. The layer can be used for system ground.
4. 35~50% of the die stage area which is exposed at back surface of package should be soldered to a part of 1^st layer.
5. The part of 1^st layer should be connected to the dedicated heat radiation layer with more than 10 thermal via holes.
Figure 8-1: Example thermal via holes on PCB.
Notes:
− Figure 8-1 is a schematic diagram showing PCB in section.
− Figure 8-2, Figure 8-3, and Figure 8-4 in the following pages are recommended land patterns for each package series.
Thermal via holes should closely be placed and aligned with lands.
− When thermal via holes cannot be with lands, the followings are recommended as represented by Figure 8-5 which is an
example for LEQ216.
− (1). Increase pattern area size as much as possible inside the package outline.
− (2). Place thermal via holes to be with lands as close as possible.
− 0.25mm ≤ a ≤ 0.30mm in Figure 8-1, Figure 8-2, Figure 8-3, and Figure 8-4
Document Number: 002-05682 Rev.*A
Page 75 of 179