S6J3200 Datasheet, PDF (133/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4.15.2 DDR-HSSPI Interface Timing (DDR Mode)
(Condition: See 8.2. Operation Assurance )
Parameter
Symbol
Pin Name
HSSPI clock cycle
G_SCLK↑ ->
delayed sample clock↑
GSDATA -> G_SCLK↑
Input setup time
G_SCLK↑ -> GSDATA
Input hold time
G_SCLK↑ -> GSDATA
Output delay time
G_SCLK↑ -> GSDATA
Output hold time
GSSEL↓ -> G_SCLK
Output delay time
tcyc
tspcnt
tisdata
tihdata
toddata
tohdata
todsel
G_SCLK0
M_SCLK0
-
G_SDATA0_0-3
G_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
G_SDATA0_0-3
G_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
G_SDATA0_0-3
G_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
G_SDATA0_0-3
G_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
G_SSEL0, 1
M_SSEL0, 1
G_SCLK↑ -> GSSEL
Output hold time
tohsel
G_SSEL0, 1
M_SSEL0, 1
Notes:
− SS2CD [1:0] should be configured as 01, 10, or 11.
Conditions
Value
Min
Max
12.5
-
0
31.5
*1
-
*1
(CL = 20pF,
IOL=-10mA,
IOH=10mA),
-
-
tcyc/4 +
1.5
Tcyc/4 -
1.0
-
-15.75+(S
S2CD+0.5)
-
*tcyc
0.75*tcyc -
2.0
-
Unit Remarks
ns
ns
ns
ns
ns
ns
ns
ns
− For *1, the delay of the delay sample clock can be configured (DLP function).
−
Document Number: 002-05682 Rev.*A
Page 133 of 179