S6J3200 Datasheet, PDF (68/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
7.2 Handling Devices
For Latch-Up Prevention
The latch-up phenomenon may occur on a CMOS IC in the following cases: the voltage applied to an input or output pin is higher
than VCC or lower than VSS; or the voltage applied between a VCC pin and a VSS pin exceeds the rating. A latch-up causes a
rapid increase in the power supply current, possibly resulting in thermal damage to an element. When using the device, take
sufficient care not to exceed the maximum rating.
Also be careful that analog power supplies (AVCC, AVRH) and analog inputs do not exceed the digital power supply (VCC) at the
analog system power-on and power-off times.
The power-on sequence is as follows. Simultaneously turn on the digital supply voltage (VCC) and analog supply voltages
(AVCC, AVRH), or turn on the digital supply voltage (VCC) and then the analog supply voltages (AVCC, AVRH).
About Handling Unused Pins
Leaving unused input pins open may cause permanent damage from a malfunction or latch-up. Take measures for unused pins,
such as pulling up or pulling down the voltage with resistors of 2 kilo ohms or higher.
If there are any unused input/output pins, set them to the output state and then open them, or set them to the input state and
handle them in the same way as input pins.
About Power Supply Pins
If the device has multiple VCC and VSS pins, the device is designed in such a way that the pins that should be at the same
potential are connected to each other inside the device to prevent malfunctions such as latch-up. However, to reduce unwanted
emissions, prevent malfunctions of strobe signals caused by an increase of the ground level, and observe standards on total
output current, be sure to connect all the VCC and VSS pins to the power source and ground externally. Also handle all the VSS
power supply pins in this way as shown in the following diagram. If there are multiple VCC or VSS systems, the device does not
operate normally even within the guaranteed operating range.
Figure 7-1 Pin Assignment
In addition, consider connecting with low impedance from the power supply source to the VCC and VSS of this device.
We recommend connecting a ceramic capacitor as a bypass capacitor between VCC and VSS, near this device.
About the Crystal Oscillation Circuit
Noise entering the X0 or X1 pin may cause a malfunction. Design the printed circuit board in such a way that the X0 and X1 pins,
the crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to the device.
We recommend that the printed circuit board artwork have the X0 and X1 pins enclosed by ground.
Document Number: 002-05682 Rev.*A
Page 68 of 179