S6J3200 Datasheet, PDF (100/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4.6.2 CSIO Timing (SMR:MD2-0=0b010)
(1) Normal Synchronous Transfer (SCR:SPI=0) and Mark Level "H" of Serial Clock Output (SMR:SCINV=0)
(Condition: See 8.2. Operation Assurance )
Parameter
Symbol
Pin Name Conditions
Value
Min
Max
Unit
Remarks
Serial clock
cycle time
tSCYC
SCK0 to SCK4,
SCK8 to
SCK12
SCK16 to
SCK17
6tCLK_LCPnA*1
-
ns
3tCLK_COMP
-
ns
SCK0 to SCK4,
SCK8 to
SCK ↓ → SOT
delay time
Valid SIN → SCK ↑
setup time
tSLOVI
tIVSHI
SCK12,
SCK16 to
SCK17
SOT0 to SOT4,
SOT8 to
SOT12,
SOT16 to
SOT17
SCK0 to SCK4,
SCK8 to
Master
Mode
(CL = 50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
-15
20
SCK12,
+15
ns
-
ns
SCK16 to
SCK ↑→ Valid SIN
hold time
tSHIXI
SCK17
SIN0 to SIN4,
SIN8 to SIN12,
0
-
ns
SIN16 to SIN17
Serial clock
"H" pulse width
tSHSL
SCK0 to SCK4,
SCK8 to
SCK12
SCK16 to
SCK17
tCLK_LCPnA*1 -5
-
ns
tCLK_COMP -5
-
ns
Serial clock
"L" pulse width
tSLSH
SCK0 to SCK4,
SCK8 to
SCK12
SCK16 to
SCK17
2tCLK_LCPnA*1
-5
-
ns
2tCLK_COMP -5
-
ns
SCK0 to SCK4,
Slave
SCK8 to
Mode
SCK12,
(CL=50pF,
SCK ↓→ SOT
delay time
SCK16 to
IOL=-2mA,
tSLOVE
SCK17
IOH=2mA),
SOT0 to SOT4, (CL=20pF,
-
SOT8 to
IOL=-1mA,
SOT12,
IOH=1mA)
20
ns
SOT16 to
SOT17
Valid SIN → SCK ↑
setup time
tIVSHE
SCK0 to SCK4,
SCK8 to
SCK12,
10
-
ns
SCK16 to
SCK ↑ → Valid SIN
hold time
tSHIXE
SCK17
SIN0 to SIN4,
SIN8 to SIN12,
10
-
ns
SIN16 to SIN17
Document Number: 002-05682 Rev.*A
Page 100 of 179