S6J3200 Datasheet, PDF (112/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4.6.4 I²C Timing (SMR:MD2-0=0b100)
(Condition: See 8.2. Operation Assurance )
Parameter
SCL clock frequency
Repeat "start"
condition hold time
SDA ↓ → SCL ↓
Symbol
fSCL
tHDSTA
Pin Name
SCL4, 10, 12,
16, and 17
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
16, and 17
Conditions
Standard
Mode
Min Max
0
100
4.0
-
High-Speed
Mode
Min Max
0
400
0.6
-
Period of "L" for
SCL clock
tLOW
SCL4, 10, 12,
16, and 17
4.7
-
1.3
-
Period of "H" for
SCL clock
Repeat "start"
condition setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
"Stop" condition setup
time
SCL ↑ → SDA ↑
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
SCL4, 10, 12,
16, and 17
4.0
-
0.6
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
(CL = 50pF,
4.7
-
0.6
16, and 17
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
16, and 17
SDA4, 10, 12,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
0
3.45^*1
0
16, and 17
SCL4, 10, 12,
250
-
100
16, and 17
SDA4, 10, 12,
16, and 17
SCL4, 10, 12,
4.0
-
0.6
16 and 17
-
-
0.9^*2
-
-
Bus-free time between
"stop" condition and
tBUF
-
4.7
-
1.3
-
"start" condition
Noise filter
tSP
-
2tCLK_
-
2tCLK_
-
COMP
COMP
Notes:
− *1: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the
SCL signal.
− *2: A high-speed mode I²C bus device can be used on a standard mode I²C bus system as long as
the device satisfies the requirement of "tSUDAT ≥ 250 ns".
− SCL4, 10, 12 and SDA4, 10, 12 only support the standard mode.
Unit
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
Remarks
Document Number: 002-05682 Rev.*A
Page 112 of 179