S6J3200 Datasheet, PDF (124/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4.12 Display Controller
8.4.12.1 Display Controller0 Timing (TTL Mode)
(Condition: See 8.2. Operation Assurance )
Parameter
Clock Cycle
Output delay from
DSP0_CLK↑
Output data valid
time
Symbol
tDC0CYC
|tDC0D|
tDC0V
Pin Name
DSP0_CLK
DSP0_DATA0_11-0
DSP0_DATA1_11-0
DSP0_CTRL11-0
DSP0_DATA0_11-0
DSP0_DATA1_11-0
DSP0_CTRL4-0
DSP0_CTRL11-0
Conditions
(CL = 20pF,
IOL=-10mA,
IOH=10mA)
(CL = 20pF,
IOL=-5mA,
IOH=5mA)
Value
Uni
Min
Max
t
12.5
-
ns
20
-
ns
-
8.5
ns
tDC0CYC-
3.2
tDC0CYC-
5.12
-
ns
-
ns
Notes:
− For *1, when used with DSP0_DATA* and DSP0_CTRL4-0 in VCC3 area.
Remarks
*1
*2
*3
*1
*2
− For *2, when used with DSP0_CTRL11-0 in VCC53 area.
− For *3, the value can be configured and adjusted.
DSP0_CLK ^VOH
DSP0_DATA0_11-0
DSP0_DATA1_11-0
DSP0_CTRL11-0
t_DC0CYC
V_OH
t_DC0D
t_DC0V
valid
Document Number: 002-05682 Rev.*A
Page 124 of 179