S6J3200 Datasheet, PDF (169/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
Summary
Error
Correct
ID
HyperBus GPO
18
Remark
Chip Select
11
Output
Revision B
12
description
MPU lock and
16
unlock value
Flash Access
17
Speed
Oscillator error 73
Input leakage
current,Pull-up
resistor,Pull-down
69
resistor and Input
capacitance for
P4_25 to P4_31
CLK_HPM
16
Frequency
nSRST description 15
HyperBus
21
,,,
-
13
Notes:
,,,
- SCL4, 10, 12 and SDA4, 10, 12 of I2C is 13
not supported yet, and will be enhanced
after Revision B.
-
18
1-wait-cycle with 80-160MHz.
19
2-wait-cycle with 160-240MHz.
− The error of source oscillator frequency
97
must be smaller than 300ppm.
Input leakage current:IIL:P2_16, 17, 19, 22,
24 to 31, P3_00 to 31, P4_00 to 12, P6_02
to 31
Input capacitance:CIN1:P0_00 to 31, P1_00 89
to 09, P2_16, 17, 19, 22, 24 to 31, P3_00 to
20, P5_21, 22, 27 to 31, P6_00 to 08, 17 to
26
1 wait cycle is necessary to read at over
18
180MHz (target).
− INITX
- SRSTX
17
- nSTRST
HyperBus
,,,
GPO signal can only be used for "Internal
Control example by GPO" in this product, #345
that is, it can select using HyperBus of PF
or using HyperBus of Graphic Sub
System.
(Part Number is added to show Chip
Select Output of MFS)
#346
Notes:
,,,
- Multi-function serial interface of the
#349
function digit 3, 4, 5, 6, 7, and 8 support
SCL4, 10, 12 and SDA4, 10, 12 of I2C
after Revision D.
To configure Lock or Unlock for both
MPUXn_UNLOCK and
MPUHn_UNLOCK,
#351
- Lock: 0x112ABB56
- Unlock: 0xACCABB56
0-wait-cycle: 80MHz or less.
1-wait-cycle: 160MHz or less.
2-wait-cycle: more than 160MHz.
#357
The maximum frequency should be
referred in datasheet.
− The error of source oscillator frequency
#360
must be smaller than 3000ppm.
Input leakage current:IIL:P2_16, 17, 19,
22, 24 to 31, P3_00 to 31, P4_00 to 12,
P4_25 to 31, P5_00 to 20, P6_02 to 31
Input capacitance:P0_00 to 31, P1_00 to #363
09, P2_16, 17, 19, 22, 24 to 31, P3_00 to
20, P4_25 to 31, P5_00 to 20, P5_21, 22,
27 to 31, P6_00 to 08, 17 to 26
See the platform manual in detail.
1 wait cycle is necessary for RAM read at
over 160MHz.
#366
No need to insert wait cycles for RAM
write.
− INITX
− SRSTX (and nSRST pin)
#367
Document Number: 002-05682 Rev.*A
Page 169 of 179