S6J3200 Datasheet, PDF (105/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
(3) SPI Supported (SCR:SPI=1), and Mark Level "H" of Serial Clock Output (SMR:SCINV=0)
(Condition: See 8.2. Operation Assurance )
Parameter
Symbol
Pin Name
Conditions
Value
Min
Max
Unit
Remarks
Serial clock
cycle time
tSCYC
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
6tCLK_LCPnA*1
-
ns
3tCLK_COMP
-
ns
SCK0 to SCK4,
SCK8 to SCK12,
SCK ↑ → SOT
delay time
tSHOVI
SCK16 to SCK17
SOT0 to SOT4,
Master
-15
SOT8 to SOT12,
SOT16 to SOT17
Mode
(CL = 50pF,
Valid SIN → SCK ↓
setup time
SCK ↓ → Valid SIN
hold time
tIVSLI
tSLIXI
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0 to SIN4,
SIN8 to SIN12,
SIN16 to SIN17
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
20
0
+15
ns
-
ns
-
ns
SOT → SCK ↓
delay time
tSOVLI
SCK0 to SCK4,
SCK8 to SCK12
SOT0 to SOT4,
SOT8 to SOT12
SCK16 to SCK17
tCLK_LCPnA*1
-15
-
ns
tCLK_COMP*1
-15
-
ns
Serial clock
"H" pulse width
tSHSL
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
tCLK_LCPnA*1 -5
-
ns
tCLK_COMP -5
-
ns
Slave
Serial clock
"L" pulse width
tSLSH
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
Mode
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
2tCLK_LCPnA*1
-5
2tCLK_COMP -5
-
-
ns
ns
SCK0 to SCK4,
SCK8 to SCK12,
IOL=-1mA,
IOH=1mA)
SCK ↑ → SOT
delay time
tSHOVE
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
-
20
ns
SOT16 to SOT17
Document Number: 002-05682 Rev.*A
Page 105 of 179