S6J3200 Datasheet, PDF (103/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
(2) Normal Synchronous Transfer (SCR:SPI=0) and Mark Level "L" of Serial Clock Output (SMR:SCINV=1)
(Condition: See 8.2. Operation Assurance )
Parameter
Symbol
Pin Name
Serial clock
cycle time
SCK ↑ → SOT
delay time
tSCYC
tSHOVI
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
Valid SIN → SCK ↓
setup time
SCK ↓ → Valid SIN
hold time
Serial clock
"H" pulse width
Serial clock
"L" pulse width
SCK ↑ → SOT
delay time
Valid SIN → SCK ↓
setup time
SCK ↓ → Valid SIN
hold time
SCK falling time
SCK rising time
tIVSLI
tSLIXI
tSHSL
tSLSH
tSHOVE
tIVSLE
tSLIXE
tF
tR
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0 to SIN4,
SIN8 to SIN12,
SIN16 to SIN17
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0 to SIN4,
SIN8 to SIN12,
SIN16 to SIN17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
*1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12
Conditions
Master
Mode
(CL = 50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
IOL=-1mA,
IOH=1mA)
Value
Min
6tCLK_LCPnA*1
3tCLK_COMP
Max
-
-
-15
+15
20
-
0
-
tCLK_LCPnA*1 -5
-
tCLK_COMP -5
-
2tCLK_LCPnA*1
-5
-
2tCLK_COMP -5
-
Slave
Mode
-
20
(CL=50pF,
IOL=-2mA,
IOH=2mA),
(CL=20pF,
10
-
IOL=-1mA,
IOH=1mA)
10
-
-
5
-
5
Unit
Remarks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
− This table provides the alternate current standard for CLK synchronous mode.
− CL is the load capability value connected to the pin at the test time.
− The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the hardware manual.
Document Number: 002-05682 Rev.*A
Page 103 of 179