S6J3200 Datasheet, PDF (131/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4.15 DDR-HSSPI
8.4.15.1 DDR-HSSPI Interface Timing (SDR Mode)
(Condition: See 8.2. Operation Assurance )
Parameter
HSSPI clock cycle
Symbol
tcyc
Pin Name
G_SCLK0
M_SCLK0
Conditions
Value
Min
Max
10
-
20
-
G_SCLK↑ ->
delayed sample clock↑
GSDATA -> G_SCLK↑
Input setup time
G_SCLK↑ -> GSDATA
Input hold time
G_SCLK↑ -> GSDATA
Output delay time
G_SCLK↑ -> GSDATA
Output hold time
GSSEL↓ -> G_SCLK
Output delay time
tspcnt
tisdata
tihdata
toddata
tohdata
todsel
-
G_SDATA0_0-3
G_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
G_SDATA0_0-3
G_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
G_SDATA0_0-3
G_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
G_SDATA0_0-3
G_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
G_SSEL0, 1
M_SSEL0, 1
G_SCLK↑ -> GSSEL
Output hold time
tohsel
G_SSEL0, 1
M_SSEL0, 1
Notes:
− SS2CD [1:0] should be configured as 01, 10, or 11.
0
31.5
*1
-
(CL = 20pF,
*1
-
IOL=-10mA,
IOH=10mA),
-
tcyc/2 + 2
tcyc/2 - 3
-
-12.00+(
SS2CD+
-
0.5)*tcyc
tcyc - 2
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
when
Quad
Page
Program
− For *1, the delay of the delay sample clock can be configured (DLP function).
Document Number: 002-05682 Rev.*A
Page 131 of 179