S6J3200 Datasheet, PDF (158/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

Summary
Error
S6J3200 Series
Correct
ID
Display controller
101
AC specification
Display controller0 Timing (TTL
mode)tDC0CYC:12.5ns (min)|tDC0D|:-
(Remarks)tDC0V:-
100
(Remarks)Notes:- ,,,,Display controller0
Timing (RSDS)|tRSD|:- (Remarks)tSPV:-
(Remarks)Notes:- ,,,,
Display controller0 Timing (TTL
mode)tDC0CYC:12.5ns (min)
*120ns(min) *2|tDC0D|:*3
(Remarks)tDC0V:*1, *4
(Remarks)Notes:- ,,,,− For *1, when used
with DSP0_DATA* and DSP0_CTRL4-0
in VCC3 area.− For *2, when used with
DSP0_DATA* and DSP0_CTRL4-0 in
VCC53 area.− For *3, the value can be
configured and adjusted.− For *4, the ^#187
value is defined as tDC0CYC - |tDC0D|
and depends on adjustment of *3.Display
controller0 Timing (RSDS)|tRSD|:*1
(Remarks)tSPV:*2 (Remarks)Notes:- ,,,,−
For *1, the value can be configured and
adjusted.− For *2, the value is defined as
tDC0CYC - |tDC0D| and depends on
adjustment of *1.
TCAP0CYC:
11.11ns (min)
Video Capture 104
tCAP0SU:
2ns (min)
Note of NC pins,
LVDS pins, and 105 -
other no-used pin
FPD-Link timing
105 -
chart
Document Number: 002-05682 Rev.*A
TCAP0CYC:
12.5ns (min)
103
tCAP0SU:
4ns (min)
#188
Note:− All the corresponding ports of
products which don't support FPD-Link
should be connected to
104
GND.AVCC3_LVDS_PLL,
#143
AVSS3_LVDS_PLL, VCC3_LVDS_Tx,
VSS3_LVDS_Tx, TxDOUTn+/-.
105, Figure: LVDS AC characteristics
106 (Timing chart)
#183
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