S6J3200 Datasheet, PDF (149/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.6 Audio DAC
8.6.1 Electrical Characteristics
(Condition: See 8.2. Operation Assurance )
Parameter
Symbol
Pin
Name
Conditions ^*1
Value
Min
Typ
Max ^{Unit Remarks}
system clock
frequency
FCLKDA0
-
-
2.048
-
18.43
2
MHz
sampling clock
fs
-
-
8
-
48 kHz
Analog output load
resistance ^*2
RL
DAC_L
-
Analog output load
capacitance ^*2
DAC_R
CL
-
capacitance
-
C_L
C_R
-
20
-
-
kΩ
-
-
100 pF
5
10
20
µF
Analog output
single-end output
range
(±full scale)
Analog output
voltage (zero)
THD+N ^*3
SNR ^*3
Dynamic range ^*3
-
DAC_L
RL=20kΩ
CL=100pF
0.673
-
AVCC3_DA
-
VP-P
C
DAC_R
0.5
-
-
-
AVCC3_DA
-
V
C
signal frequency:
-
-
1kHz
-
-82
-72
dB
LPF(fc: 20kHz)
-
-
signal frequency:
85
89
-
dB
1kHz
-
-
LPF(fc: 20kHz)—
83
86
-
dB
— A-weighting filter
Out-of-Band Energy
-
-
20kHz to 64fs
-
-
-33
dB
Channel Separation
-
-
-
-
80
-
dB
Output impedance
-
-
-
150
200
250
Ω
PSRR
digital ^{noise 50Hz}
-
input: noise 1kHz
-
-
-
zero _{noise 20kHz}
-
-35
-
dB
-50
-
dB
-40
-
dB
digital input :full scale
sine
-
-13
-
dB
Supply current
normal operation
-
AVCC3
_DAC
-
-
2.2
3.2 mA
Supply current
power-down
Startup Time ^*4
-
AVCC3
_DAC
-
-
-
DAE↑
-
-
100 µA
-
650 ^*5
-
ms
Notes:
− *1: All parameters specified fs=44.1 kHz, system clock 256fs and 16-bit data, RL-20kΩ, CL=100pF, unless otherwise noted.
− *2: Refer to bellow note on RL load connection.
− *3: These values do not include the noise caused by the analog power supply. (Refer to 7. Use examples)
− *4: 10µF is connected to C_L, C_R.
− *5: Startup time (Figure 8-8)
Document Number: 002-05682 Rev.*A
Page 149 of 179