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S6J3200 Datasheet, PDF (29/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family
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S6J3200 Series
Figure 4-11: TEQFP-208 (S6J326CLxx)
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DSP0_CLK+
DSP0_CLK-
DSP0_DATA_D0+
DSP0_DATA_D0-
DSP0_DATA_D1+
DSP0_DATA_D1-
DSP0_DATA_D2+
DSP0_DATA_D2-
DSP0_DATA_D3+
DSP0_DATA_D3-
0
0
DSP0_DATA_D5+
DSP0_DATA_D5-
DSP0_DATA_D6+
DSP0_DATA_D6-
DSP0_DATA_D7+
DSP0_DATA_D7-
DSP0_DATA_D8+
DSP0_DATA_D8-
0
VSS
AVSS
DAC_R
C_R
AVSS
AVCC3_DAC
DAC_L
C_L
AVSS
VSS
VCC12
AVSS_LVDS_PLL
AVCC3_LVDS_PLL
VCC3_LVDS_Tx
VSS_LVDS_Tx
TxDOUT3+
TxDOUT3-
TxDOUT2+
TxDOUT2-
TxCLK+
TxCLK-
TxDOUT1+
TxDOUT1-
TxDOUT0+
TxDOUT0-
VSS_LVDS_Tx
VCC3_LVDS_Tx
VCC12
VSS
VCC3
DSP0_CTRL1
DSP0_CLK
DSP0_CTRL2
DSP0_DATA0_0
DSP0_DATA1_0
DSP0_DATA0_1
DSP0_DATA1_1
DSP0_DATA0_2
DSP0_DATA1_2
DSP0_DATA0_3
DSP0_DATA1_3
VSS
VCC3
DSP0_DATA0_5
DSP0_DATA1_5
DSP0_DATA0_6
DSP0_DATA1_6
DSP0_DATA0_7
DSP0_DATA1_7
DSP0_DATA0_8
DSP0_DATA1_8
VSS
-1
-2
A3
A4
-5
-6
A7
A8
-9
- 10
- 11
- 12
- 13
- 14
- 15
B 16
B 17
B 18
B 19
B 20
B 21
B 22
B 23
B 24
B 25
- 26
- 27
- 28
- 29
- 30
C 31
D 32
D 33
D 34
D 35
D 36
D 37
D 38
D 39
D 40
D 41
- 42
- 43
D 44
D 45
D 46
D 47
D 48
D 49
D 50
D 51
- 52
○
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TOP VIEW
TEQFP-208
156 -
155 -
154 S
153 S
152 S
151 S
150 S
149 S
148 S
147 S
146 -
145 -
144 S
143 S
142 S
141 S
140 S
139 S
138 S
137 S
136 -
135 -
134 S
133 S
132 S
131 S
130 S
129 S
128 S
127 S
126 -
125 -
124 -
123 -
122 -
121 -
120 -
119 -
118 H
117 -
116 -
115 -
114 Q
113 P
112 N2
111 N2
110 N2
109 O
108 N
107 M
106 M
105 -
DVCC
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DVSS
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AN49
SIN4 TX1 PWM2M5 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT12 P4_12
AN48
SCK4 RX1 PWM2P5 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT11 P4_11
AN47
SOT4 0
PWM1M5 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT10 P4_10
AN46
0
0
PWM1P5 OCU4_OTD1 ICU4_IN1 PPG4_TOUT2 EINT9 P4_09
AN45
SIN3 0
PWM2M4 OCU4_OTD0 ICU4_IN0 PPG4_TOUT0 EINT8 P4_08
AN44
SCK3 0
PWM2P4 OCU3_OTD1 ICU3_IN1 PPG3_TOUT2 EINT7 P4_07
AN43
SOT3 0
PWM1M4 OCU3_OTD0 ICU3_IN0 PPG3_TOUT0 EINT6 P4_06
AN42
0
0
PWM1P4 OCU2_OTD1 ICU2_IN1 PPG2_TOUT2 EINT5 P4_05
DVCC
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0
DVSS
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0
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0
AN41
SIN2 0
PWM2M3 OCU2_OTD0 ICU2_IN0 PPG2_TOUT0 EINT4 P4_04
AN40
SCK2 0
PWM2P3 OCU1_OTD1 ICU1_IN1 PPG1_TOUT2 EINT3 P4_03
AN39
SOT2 0
PWM1M3 OCU1_OTD0 ICU1_IN0 PPG1_TOUT0 EINT2 P4_02
AN38
0
0
PWM1P3 OCU0_OTD1 ICU0_IN1 PPG0_TOUT2 EINT1 P4_01
MFS0_CS2
MFS0_CS1
MFS0_CS3
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MFS2_CS1
MFS2_CS0
MFS0_CS0
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MFS4_SCL
MFS4_SDA
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AN37
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PWM2M2 OCU0_OTD0 ICU0_IN0 PPG0_TOUT0 EINT0 P4_00
AN36
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0
PWM2P2 OCU11_OTD1 ICU11_IN1 PPG11_TOUT2 EINT15 P3_31
AN35
0
0
PWM1M2 OCU11_OTD0 ICU11_IN0 PPG11_TOUT0 EINT14 P3_30
AN34
0
0
PWM1P2 OCU10_OTD1 ICU10_IN1 PPG10_TOUT2 EINT13 P3_29
DVCC
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0
DVSS
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0
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0
0
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AN33
0
BN1(BL1P)WM2M1 OCU10_OTD0 ICU10_IN0 PPG10_TOUT0 EINT12 P3_28
AN32
0
BP1(BH1P)WM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27
AN31
0
AN1(AL1P)WM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26
AN30
0
AP1(AH1P)WM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25
AN29
0
BN0(BL0P)WM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24
0
00000
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0
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AN28
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BP0(BH0P)WM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23
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00000
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0
0
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AN27
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AN0(AL0P)WM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22
0
00000
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0
0
0
0
0
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AN26
0
AP0(AH0P)WM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21
DSP0_DATA1_10
00000
P5_21 EINT3
PPG9_TOUT2 ICU9_IN1 OCU9_OTD1
0
DSP0_DATA0_4 MDC CAP0_DATA0
DVCC
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0
0
0
0
0
0
0
DSP0_DATA0_11
00000
P0_18 EINT15
PPG3_TOUT2 ICU3_IN1 OCU3_OTD1
0
0 MDIO CAP0_DATA1
DVSS
0
0
0
0
0
0
0
0
DSP0_DATA1_11
00000
P0_19 EINT0
PPG4_TOUT0 ICU4_IN0 OCU4_OTD0
0
DSP0_DATA1_4
0 CAP0_DATA2
VSS
0
0
0
0
0
0
0
0
0
00000
P5_27 EINT11
PPG9_TOUT2 ICU9_IN1 OCU9_OTD1
0
TOT0
0 CAP0_DATA3
VCC12
0
0
0
0
0
0
0
0
0
00000
P5_28 EINT12
PPG10_TOUT0 ICU10_IN0 OCU10_OTD0
0
TIN0
0 CAP0_DATA4
VCC12
0
0
0
0
0
0
0
0
0
00000
P5_29 EINT13
PPG10_TOUT2 ICU10_IN1 OCU10_OTD1
0
TOT1
0 CAP0_DATA5
AVSS
0
0
0
0
0
0
0
0
0
00000
P5_30 EINT14
PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0
TIN1
0 CAP0_DATA6
AVRH5
0
0
0
0
0
0
0
0
0
00000
P5_31 EINT15
PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0
TOT2
0 CAP0_DATA7
AVCC5
0
0
0
0
0
0
0
0
0
00000
P6_00 EINT0
PPG0_TOUT0 ICU0_IN0 OCU0_OTD0
0
TIN2
0 CAP0_DATA8
ADTRG
0
SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18
0
00000
P0_00 EINT1
PPG0_TOUT2 ICU0_IN1 OCU0_OTD1
0
TOT3
0 CAP0_DATA9
C
0
0
0
0
0
0
0
0
0
00000
P0_01 EINT2
PPG1_TOUT0 ICU1_IN0 OCU1_OTD0
0
TIN3 TXEN CAP0_DATA10
VSS
0
0
0
0
0
0
0
0
0
00000
0
0
0
0
0
0
0
0
0
VCC5
0
0
0
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0
0
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0
00000
0
0
0
0
0
0
0
0
0
RSTX
0
0
0
0
0
0
0
0
CAP0_DATA11
G_CK_2 0 0 0 0
P0_04 EINT5
PPG2_TOUT2 ICU2_IN1 OCU2_OTD1
0
TOT17 TXD0 CAP0_DATA13
MODE
0
0
0
0
0
0
0
0
CAP0_DATA12 G_DQ3_2 0 0 0 0
P0_05 EINT6
PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0
TIN17 TXD1 CAP0_DATA14
JTAG_TMS 0
0
0
0
0
0
0
0
CAP0_DATA13 G_DQ2_2 0 0 0 0
P0_06 EINT7
PPG3_TOUT2 ICU3_IN1 OCU3_OTD1
0
TOT18 TXD2 CAP0_DATA15
JTAG_TCK 0
0
0
0
0
0
0
0
CAP0_DATA14 G_DQ1_2 0 0 0 0
P0_07 EINT8
PPG4_TOUT0 ICU4_IN0 OCU4_OTD0
0
TIN18 TXD3 CAP0_DATA16
JTAG_TDI
0
0
0
0
0
0
0
0
CAP0_DATA15 G_DQ0_2 0 0 0 0
P0_08 EINT9
PPG4_TOUT2 ICU4_IN1 OCU4_OTD1
0
TOT19 RXD0 CAP0_DATA17
JTAG_TDO 0
0
0
0
0
0
0
0
0 G_CS#1_2 0 0 0 0
P0_09 EINT10
PPG5_TOUT0 ICU5_IN0 OCU5_OTD0
0
TIN19 RXD1 CAP0_DATA18
JTAG_NTRST 0
0
0
0
0
0
0
0
0 G_RWDS_2 0 0 0 0
P0_10 EINT11
PPG5_TOUT2 ICU5_IN1 OCU5_OT ID21S0_ECLK
TOT32 RXD2 CAP0_DATA19
X0
0
0
0
0
0
0
0
0
0 G_CS#2_2 0 0 0 0
P0_11 EINT12
PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD
TIN32 RXD3 CAP0_DATA20
X1
0
0
0
0
0
0
0
0
0
00000
0
0
0
0
0
0
0
0
0
VSS
0
0
0
0
0
0
0
0
Notes:
− The pins which are described in "red" character are not supported for product with revision A and C.
Document Number: 002-05682 Rev.*A
Page 29 of 179
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