S6J3200 Datasheet, PDF (161/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
Summary
Error
Correct
ID
Original document code: DS708-00003-0v02-E, Previous document code: DS708-00003-0v01-E
Rev. 2.0 May 20, 2015
Notes;
- ,,,
Note for Basic
11
Option
Notes;
- ,,,
− The CLK_CPU is assigned for CPU
11
#194
clock. The CLK_CD3A0 is assigned for
Graphic clock. They are defined at the
chapter of Clock Configuration.
Power domain (PD):
----
See the platform manual and chapter
STATE TRANSITION in detail.
Power domain
15
-
reset
The product series supports the power off
15
control of PD1, PD2 (including PD3 and #175
5), and PD6.
The power domain resets of PD3 and
PD5 included in PD2 are not supported in
the product series, and "0" is always read
from the reset factor flags of them.
Original document code: DS708-00003-0v03-E, Previous document code: DS708-00003-0v02-E
Rev. 1.0 May 20, 2015
Display output 10
Number of display outputs:
2 outputs simultaneously
10
Selectable from 2 x DRGB, 1 x RSDS, or 1 x
LVDS (FPD-Link)
Number of display outputs:
Option
Maximum 2 outputs simultaneously
#210
Notes;- ,,,,- ,,,,− Display Output ch.0 is
used for RSDS and FPD-LINK (LVDS) as
well as DRGB (Digital RGB). The ch.0 of
Display output 11
Notes;- ,,,,- ,,,,
12
the product which doesn’t support
#211
FPD-LINK is used for RSDS and DRGB.
Display Output ch.1 is used for DRGB
only.
Note:
- ,,,
- The function digit A, B, C, and D supports
Revision B
description
Hyper SRAM. Its 3, 4, 5, and 6 doesn’t
Note:
support Hyper
- ,,,
SRAM. Hyper Bus interface ch.2 on graphic
11
12
- HyperBus Interface ch.1 of the function #267
sub system will be embedded on product
digit 3, 4, 5, and 6 support HyperRAM
which is
after Revision B.
specified with function digit 7and 8 after
revision B. Revision A only has ch.0 and 1
of Hyper Bus
interface.
Document Number: 002-05682 Rev.*A
Page 161 of 179