S6J3200 Datasheet, PDF (137/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4.16.3 Hyper Bus Read Timing (HyperFlash)
Parameter
Symbol
Pin Name
Conditions
Hyper Bus clock cycle
tRDSCYC
G_CK,
G_RWDS
M_CK,
M_RWDS
CS↑↓ -> CK↑
Chip Select setup time
tCSS
G_CS#_1,2
M_CS#_1,2
DQ -> CK↑↓
Setup time
CK↑↓ -> DQ
Hold time
tIS
G_DQ7-0
M_DQ7-0
(CL = 20pF,
IOL=-10mA,
tIH
G_DQ7-0
M_DQ7-0
IOH=10mA),
CK↓ -> CS↑
Chip select hold time
tCSH
G_CS#_1,2
M_CS#_1,2
RDS↑↓> DQ
Setup time
tDSS
G_DQ7-0
M_DQ7-0
RDS↑↓> DQ
Hold time
tDSH
G_DQ7-0
M_DQ7-0
− (A): The value is targeted by the product series with revision digit A.
− (B): The value is targeted by the product series with revision digit B.
(Condition: See 8.2. Operation Assurance )
Value
Min
Max
12.5
-
Uni Remark
t
s
ns
(A)
10
-
ns
(B)
tRDSCYC
-3.25
-
tRDSCYC -2.0
1.25
-
ns
(A)
ns
(B)
ns
1.25
-
ns
tRDSCYC / 2
-
ns
-0.8
-
ns
-0.8
-
ns
t_ACC
G_CS#_1,2
M_CS#_1,2
V_OL
G_CK
t_CSS
V_OH
M_CK
V_OL
t_DSV
G_RWDS
M_RWDS
G_DQ7~0
M_DQ7~0
t_IS
t_IH
V_IH
CA0 CA0 CA1 CA1 CA2 CA2
47-40 39- 31-24 23-16 15-8 7-0
32
V_IL
t_DQLZ
V_OH
t_CSHI
t_CSH
t_CSS
t_CKDS
t_RDSCYC
V_OH
t_DSZ
t_OZ
t_DSH
t_DSS
V_OH
Dn
Dn
15-8 7-0
Dn+1
15-8
Dn+1
7-0
V_OL
Document Number: 002-05682 Rev.*A
Page 137 of 179