S6J3200 Datasheet, PDF (138/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
8.4.16.4 Hyper Bus Read Timing (HyperRAM)
Parameter
Symbol
Pin Name Conditions
Hyper Bus clock cycle
tRDSCYC
G_CK,
G_RWDS
M_CK,
M_RWDS
CS↑↓ -> CK↑
Chip Select setup time
tCSS
G_CS#_1,2
M_CS#_1,2
DQ -> CK↑↓
Setup time
tIS
G_DQ7-0
M_DQ7-0
CK↑↓ -> DQ
Hold time
CK↓ -> CS↑
Chip select hold time
tIH
G_DQ7-0
M_DQ7-0
(CL = 20pF,
tCSH
G_CS#_1,2
M_CS#_1,2
IOL=-10mA,
IOH=10mA),
RWDS↑↓> DQ (valid)
Setup time
tDSS
G_DQ7-0
M_DQ7-0
RWDS↑↓> DQ (invalid)
Hold time
tDSH
G_DQ7-0
M_DQ7-0
CK↑ -> RWDS↑↓
Refresh Indicator Valid
tRIV
G_RWDS
M_RWDS
CK↑ -> RWDS(Hi-z)
Refresh Indicator Hold
tRIH
G_RWDS
M_RWDS
Notes:
− (A): The value is targeted by the product series with revision digit A.
− (B): The value is targeted by the product series with revision digit B.
(Condition: See 8.2. Operation Assurance )
Value
Min
Max
12.5
-
Unit Remarks
ns
(A)
10
-
ns
(B)
tRDSCYC -3.25
-
tRDSCYC -2.0
-
1.25
-
ns
(A)
ns
(B)
ns
1.25
-
ns
tRDSCYC /2
-
ns
-0.8
-
ns
-8
-
ns
-
6
ns
0
-
ns
G_CS#_1,2
M_CS#_1,2
G_CK
M_CK
G_RWDS
M_RWDS
G_DQ7~0
M_DQ7~0
t_RWR
V_OL
t_CSS
t_RIV
V_OH
V_OL
t_RIH
t_CSM
t_PO
t_IH
t_IS
V_IH
CA0 CA0 CA1 CA1 CA2 CA2
47-40 39- 31-24 23-16 15-8 7-0
32
V_IL
t_DQLZ
V_OH
t_CSHI
t_CSH
t_CSS
t_RDSCYC
t_CKDS
V_OH
t_DSZ
t_OZ
t_DSH
V_OH
t_DSS
Dn
Dn
15-8 7-0
Dn+1
15-8
Dn+1
7-0
V_OL
Document Number: 002-05682 Rev.*A
Page 138 of 179