S6J3200 Datasheet, PDF (13/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo꽬 Family

S6J3200 Series
3. Product Description
3.1 Overview
This chapter explains the product features of S6J3200 series. The description of this chapter should precede the duplicated
description on platform manual.
3.2 Product Description
The table shows features.
Table 3-1
Feature
Description
Technology
Functional Safety
Peripherals
Power Domain (PD)
Debug and Trace
System Control
Clock
Embedded CR oscillation
Clock Supervisor
Reset
Hardware Watchdog
Software Watchdog
55nm CMOS technology with embedded FLASH
Fully automotive qualified according to ISO/TS 16949 and AEC-Q100
The product series has some functional safety features suited for ASIL-B application.
See function list.
See the platform manual and chapter STATE TRANSITION in detail.
The product series supports the power off control of PD1, PD2 (including PD3 and 5), and PD6.
The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series,
and "0" is always read from the reset factor flags of them.
This series doesn't support partial wakeup for PD6.
See the platform manual in detail.
− Standard 5-pin JTAG interface
− 4k Word Embedded Trace Buffer
4-bit trace support for TEQFP package.
Full trace (dedicated 16-bit port) with special bond-out package is planned.
See the platform manual in detail.
Main and sub oscillator is available.
− A wide range of 3.6 - 16MHz is available for main oscillator
− 32KHz is available for sub oscillator
Sub clock is enable/disable by register settings
See the platform manual in detail.
CLK_CLKO (Clock Output Function) is not supported.
See the platform manual in detail.
Stabilization time is as followings.
− 5us for 4MHz (Fast clock)
− 20us for 100kHz (Slow clock)
See the platform manual in detail.
This product series doesn’t support clock supervisor output port. (Related register and internal
circuit is implemented.)
See the platform manual in detail.
Following resets are not mounted on this device.
− INITX
− SRSTX (and nSRST pin)
See the platform manual in detail.
Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the bit
ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK=1).
The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and
internal circuit is implemented.)
See the platform manual in detail.
The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and
internal circuit is implemented.)
Document Number: 002-05682 Rev.*A
Page 13 of 179