AK4558EN Datasheet, PDF (86/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
Addr Register Name D7
D6
D5
D4
D3
D2
D1
D0
04H Control 2
0
0
0 MCKS1 MCKS0 DFS1 DFS0 ACKS
R/W
RD
RD
RD R/W R/W R/W R/W R/W
Default
0
0
0
1
0
0
0
0
ACKS: Automatic Clock Recognition Mode
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
When ACKS bit = “1”, master clock frequency is detected automatically. In this case, the setting of
DFS1-0 bits is ignored. When ACKS bit = “0”, DFS1-0 bits set the sampling speed mode. The MCKI
frequency of each mode is detected automatically.
DFS1-0: Sampling Speed Control (Table 8)
The setting of DFS1-0 bits is ignored when ACKS bit =“1”.
MCKS1-0: Master Clock Input Frequency Select (Table 9)
Addr Register Name D7
05H Mode Control
0
R/W
RD
Default
0
D6
D5
D4
D3
D2
D1
D0
FS3 FS2 FS1 FS0 BCKO1 BCKO0 LOPS
R/W R/W R/W R/W R/W R/W R/W
0
1
0
1
0
1
0
LOPS: Power-save Mode of LOUT/ROUT
0: Normal Operation (default)
1: Power-save Mode
BCKO1-0: BICK Output Frequency Setting in Master Mode (Table 21)
Default: “01” (64fs)
FS3-0: Sampling Frequency (Table 17, Table 18)
Default: “0101”
015004500-E-02
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2015/09