AK4558EN Datasheet, PDF (75/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
3. DAC Output
3-1. PS pin = “L”
FS3-0 bits
(Addr 05H,D6-3)
SSLOW
SLDA, SDDA bits
(Addr 06H, D4-2)
ATL/ATR7-0 bits
(Addr 08H&09H)
0111
(1)
09H
FFH
LOPS bit
(Addr 05H,D0)
PMDAL/R bits
(Addr:00H D2&D1)
LOUT pin
ROUT pin
0111
09H
(2)
FFH
(3)
>300 ms
(4) ₍₅₎
(6)
>300 ms
(7)
(9)
(8)
<300 ms
Normal Output
<300 ms
Figure 59. DAC Sequence (PS pin =”L”)
Example:
PLL, Master Mode
Audio I/F Format :32bit I2S (DAC)
Digital filter: Short delay Sharp Roll-off
Sampling Frequency:44.1KHz
Digital Volume: 0dB
(1) Addr:05H, Data: 3AH
(2) Addr:06H, Data: 09H
(3) Addr:08H/09H, Data: FFH
(4) Addr:05H, Data: 3BH
(5) Addr:00H, Data: 07H
(6) Addr:05H, Data: 3AH
Playback
(7) Addr:05H, Data: 3BH
(8) Addr:00H, Data: 01H
(9) Addr:05H, Data:3AH
<Sequence>
Following is the example when fs=44.1k.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). The DAC must be powered-up in consideration of PLL
lock time.
(2) Set up the digital filter mode.
(3) Set up the digital output volume (Address = 08H, 09H).
(4) Set the DAC output to power-save mode: LOPS bit “0” → “1”
(5) Power up the DAC: PMDAL = PMDAR bits = “0” → “1”
Outputs of the LOUT and ROUT pins start rising. Rise time is 300ms (max.) when C = 1µF.
(6) Release power-save mode of the DAC output: LOPS bit = “1” → “0”
Set LOPS bit to “0” after the LOUT and ROUT pins output “H”. Sound data will be output from the
LOUT and ROUT pins after this setting.
(7) Set the DAC output power-save mode: LOPS bit = “0” → “1”
(8) Power down the DAC: PMDAL = PMDAR bits = “1” → “0”
Outputs of the LOUT and ROUT pins start falling. Fall time is 300ms (max.) when C = 1µF.
(9) Release power-save mode of the DAC output: LOPS bit = “1” → “0”
Set LOPS bit to “0” after outputs of the LOUT and ROUT pins fall to “L”.
015004500-E-02
- 75 -
2015/09