AK4558EN Datasheet, PDF (78/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
5. Stop of Clock
Necessary clocks must be supplied when the AK4558 is in operation.
1. PLL Master Mode
PMPLL bit
(Addr:01H, D0)
External MCKI
Input
(1)
(2)
Example:
Audio I/F Format: 32bit I2S (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1) Addr:01H, Data:00H
(2) Stop an external MCKI
Figure 62. Clock Stopping Sequence (1)
<Example>
(1)Power down PLL: PMPLL bit = “1”  “0”
(2)Stop an external master clock.
2. PLL Slave Mode (BICK, LRCK pin)
PMPLL bit
(Addr:01H, D0)
External BICK
Input
(1)
(2)
Example
A: udio I/F Format : 32bit I2S (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 63. Clock Stopping Sequence (2)
<Example>
(1)Power down PLL: PMPLL bit = “1”  “0”
(2)Stop the external BICK and LRCK clocks
3. EXT Slave Mode
External MCKI
Input
External BICK
Input
External LRCK
Input
(1)
Example
: ^{Audio I/F Format : 32bit I2S (ADC & DAC)}
(1)
Input MCKI frequency:256fs
(1) Stop the external clocks
(1)
Figure 64. Clock Stopping Sequence (3)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
015004500-E-02
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2015/09