AK4558EN Datasheet, PDF (71/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

1-2. PLL Slave Mode with External Clock (BICK pin, LRCK pin)
(PS pin=“L”, CKS3-2 pins = “L L” or “L H” or “H L”)
[AK4558]
Power Supply
PDN pin
Internal PDN
PMPLL bit
(Addr:01H, D0)
BICK pin
LRCK pin
Internal Clock
(1)
(2)
1ms (min) (LDOE=”L”), 10ms (min) (LDOE=”H”)
(3)
(4)
Input
BICK…2ms (max)
LRCK…40ms (max)
(5)
Example:
Audio I/F Format: 32bit I2S (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
4f₍s₁₎of_{Power Supply & PDN pin = “L”  “H”}
(3)Addr:01H, Data:04H
Addr:03H, Data:38H
Addr:05H, Data:22H
(4) Addr:01H, Data:05H
Figure 54. Clock Set Up Sequence (2)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4558.
(2) Control register settings become available in 10ms (min.) when LDOE pin = “H”, or 1ms (min.)
when LDOE pin = “L”, after the PDN pin “L” → “H”. The power-up time of VCOM will be 2ms
(max.) after the PDN pin “L” → “H” if the external capacitor is 1μF±50%.
(3) DIF2-0, PLL3-0, FS3-0 and BCKO1-0 bits must be set during this period.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK or LRCK
pin) is supplied. PLL lock time is 2ms (max) when BICK is a PLL reference clock. PLL lock time is
40ms (max) when LRCK is a PLL reference clock.
(5) Normal operation starts after that the PLL is locked.
015004500-E-02
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2015/09