AK4558EN Datasheet, PDF (35/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
■ System Clock
There are four clock modes to interface with external devices (Table 3, Table 4).
Mode
PMPLL bit CKS3-2 pins PLL3-0 bits
PLL Master Mode
1
“HH”
Table 16
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
1
“LL”
“LH”
Table 16
EXT Slave Mode
0
“HL”
x
EXT Master Mode
0
“HH”
x
Table 3. Clock Mode Setting (x: Don’t care)
Figure
Figure 14
Figure 16
Figure 12
Figure 13
PS pin
“H”
Parallel
Mode
“L”
Serial
Mode
Mode
MCKI pin
BICK pin
EXT Slave Mode
Selected by CKS3-0 pins
Input
( 32fs)
EXT Master Mode
Selected by CKS3-0 pins
Output
(64fs)
Output
PLL Master Mode
Selected PLL3-0 bits
(Selected by
BCKO1-0 bits)
PLL Slave Mode
(PLL Reference Clock:
Connect to VSS2
Input
(Selected by
LRCK or BICK pin)
PLL3-0 bits)
EXT Slave Mode
ACKS bit = “1”
or
ACKS bit = “0” and
DFS1-0 bits
Input
( 32fs)
EXT Master Mode
Selected by MCKS1-0
bits and DFS1-0 bits
Output
(Selected by
BCKO1-0 bits)
Table 4. Clock Pin States in Clock Mode
LRCK pin
Input
(1fs)
Output
(1fs)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
015004500-E-02
- 35 -
2015/09