AK4558EN Datasheet, PDF (83/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
S
T
A
R/W ="0"
R
T
S
T
A
R/W ="1"
R
T
SDA
Slave
S _Address
Sub
Address(n)
Slave
S _Address
Data(n)
Data(n+1)
A
A
A
MA
MA
C
K
C
K
C
K
AC
S
T
K
A
S
T
C
K
E
E
R
R
Figure 73. Random Address Read
S
T
O
P
Data(n+x)
P
MA
MN
A
S
T
C
K
A
S
T
A
C
E
EK
R
R
SDA
SCL
S
start condition
P
stop condition
Figure 74. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
SCL FROM
MASTER
S
START
CONDITION
not acknowledge
1
2
Figure 75. Acknowledge (I²C Bus)
acknowledge
8
9
clock pulse for
acknowledgement
SDA
SCL
015004500-E-02
data line
stable;
data valid
change
of data
allowed
Figure 76. Bit Transfer (I²C Bus)
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2015/09