AK4558EN Datasheet, PDF (54/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
b) DAC
(1) TDM256 Mode (Normal, Double Mode)
By setting TDM1-0 bits = “1X” and SDS1-0 bits, eight channel outputs can be supported at maximum.
The SDTI input data of the AK4558 #1, #2, #3 and #4 can be selected as DAC TDM data by SDS1-0 bits
(Table 24). LOUT/ROUT pins of each device output the data set by SDS1-0 bits as shown in Figure 31.
256fs
48kHz, 96kHz
256fs
AK4558 #1
MCKI
SDTI
LRCK CAD1-0
BICK ^=00H
LOUT
ROUT
8ch TDM
AK4558 #2
MCKI
SDTI
LRCK CAD1-0
BICK ^=01H LOUT
ROUT
AK4558 #3
MCKI
SDTI
LRCK CAD1-0
=10H
BICK
LOUT
ROUT
LRCK
AK4558 #4
MCKI
SDTI
LRCK CAD1-0
=11H
BICK
LOUT
ROUT
Figure 30. Cascade TDM256 Connection Diagram
256 BICK
BICK(256fs)
SDTI 1,2,3,4
31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30
Data1
32 BICK
Data2
32 BICK
Data3
32 BICK
Data4
32 BICK
Data5
32 BICK
Data6
32 BICK
Data7
32 BICK
Data8
32 BICK
SDTI#1 (i)
SDTI#2 (i)
31 30 1 0 31 30 1 0
L#1
32 BICK
R#1
32 BICK
31 30
SDTI#3 (i)
SDTI#4 (i)
31 30 1 0 31 30 1 0
L (Data1) R (Data2)
32 BICK 32 BICK
31 30 1 0 31 30 1 0
L (Data3) R (Data4)
32 BICK 32 BICK
31 30
31 30
31 30 1 0 31 30 1 0
L (Data5) R (Data6)
32 BICK 32 BICK
31 30
31 30 1 0 31 30 1 0 31 30
L (Data7) R (Data8)
32 BICK 32 BICK
Figure 31. Cascade TDM Timing (Mode 22; TDM256 mode, MSB justified, Slave mode)
015004500-E-02
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2015/09