AK4558EN Datasheet, PDF (74/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
2. ADC Output
2-1. PS pin = “L”
FS3-0 bits
(Addr:05H, D6-3)
0111
(1)
TDM1-0,DIF2-0 bits
(Addr:03H D7-6&D5-3)
38H
(2)
0111
38H
Example:
PLL Master Mode
Audio I/F Format :32bit I2S
Sampling Frequency: 44.1kHz
Digital filter:
Short delay Sharp Roll-off
(1) Addr:05H, Data:3AH
(2) Addr:03H, Data:38H
SLAD,SDAD bits
(Addr:07H D3&D2)
PMADL/R bits
(Addr:00H, D4-3)
SDTO pin
State
0FH
(3)
“L” Output
0FH
(4)
(5)
5200/fs
Initialize
Normal
State
“L” Output
(3) Addr:07H, Data:0FH
(4) Addr:00H, Data:19H
Recording
(5) Addr:00H, Data:01H
Figure 57. ADC Output Sequence (PS pin = “L”)
<Sequence>
In the case of fs=44.1kHz
At first, clocks should be supplied according to “Serial Mode”.
(1) Set up the sampling frequency (FS3-0 bits). The ADC must be powered-up in consideration of PLL
lock time.
(2) Set up the audio format (Addr=03H).
(3) Set up the de-emphasis filter (Addr = 07H).
(4) Power up the ADC: PMADL = PMADR bits = “0” → “1”
Initialization cycle of the ADC is 5200/fs @Normal mode. The SDTO pin outputs “L” during
initialization.
(5) Power down ADC: PMADL = PMADR bits = “1” → “0”
2-2. PS pin = “H”
CKS3-0 pins
PMADL/R pins
XXXX
(1)
(2)
5200/fs
SDTO pin
State
“L” Output
Initialize
Normal
State
“L” Output
Figure 58.ADC Output Sequence (PS pin =“H”)
<Sequence>
At first, operation mode should be set by CKS3-0 bits according to “Parallel Mode”.
(1) Power up the ADC: PMADL pin = PMADR pin = “L” → “H”
Initialization cycle of the ADC is 5200/fs @Normal mode. The SDTO pin outputs “L” during
initialization.
(2) Power down ADC: PMADL pin = PMADR pin = “H” → “L”
015004500-E-02
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2015/09